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700 mhz to 2700 mhz rx mixer with integrated if dga, fractional - n pll, and vco data sheet adrf6620 rev. 0 document feedback information fur nished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subjec t to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwo od, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com features integrated fractional - n phase - locked loop ( pll ) rf input frequency range: 700 mhz to 2700 mhz internal l ocal oscillator (lo) frequency range: 350 mhz to 2850 mhz input p1db: 17 dbm output ip3: 45 dbm single - pole four - throw (sp4t) rf input switch digital step a ttenuator (dsa) range : 0 db to 15 db integrated rf tunable balun allowing single - ended 50 ? input multicore integrated voltage controlled oscillator ( vco ) digitally programmable variable gain amplifier ( dga ) ?3 db bandwidth: > 600 mhz balanced 150 ? if output impedance programmable via 3 - wire serial port interface ( spi ) single 5 v supply applic ations wireless r eceivers digital predistortion (dpd) r eceivers functional block dia gram lock_det vp ta t loin? vtune loin+ 1, 2, 4, 8 charge pum p cp n = int + refin muxout rfin0 ifout1? mxout+ cs sclk sdio mxout? ifin+ ifin? loin+ loin? vtune cp seria l port inter f ace ldo vco ldo 3.3v ifout1+ ifout2? ifout2+ ldo 2.5 v rfsw0 rfsw1 rfin1 rfin2 rfin3 2 8 4 2 1 2 + pfd frac mod 1 1489-001 decl2 decl4 decl1 figure 1. general description the adrf6620 is a highly integrated activ e mixer and synthesizer that is ideally suited for wireless receiver sub system s. the feature rich device consists of a high linearity broadband active mixer; an integrated fractional - n pll; lo w phase noise, multicore vco; and if dga . in addition, the adrf6620 integrates a 4:1 rf switch, an on - chip tunable rf balun, programmable rf attenuator, and low dropout ( ldo ) regulator s. this high ly integrated device fits within a small 7 mm 7 mm footpr int. the high isolation 4:1 rf switch and on - chip tunable rf balun enable the adrf6620 to support four single - ended 50 ? terminated rf inputs. a pro grammable attenuator ensures optimal rf input drive to the high linearity mixer core . the integrated dsa has an attenuatio n range of 0 db to 15 db with a step size of 1 db . the adrf6620 offers two alternatives for generating the dif - ferential lo input signal: externally , via a high frequency , low phase noise lo signal , or internally , via the on - chip f ractional -n pll synthesizer. the integrated synthesizer enables continuous lo coverage from 350 mhz to 2850 mhz. the pll reference input can support a wide frequency range because the divide and multipl y blocks can be used to increase or decrease the reference frequency to the desired value before it is passed to the p hase frequency detector (pfd). t he integrated high linearity dga provides an additional gain range from 3 db to 1 5 db in steps of 0.5 db for maximum flexibility in driving an analog - to - digital converter ( adc ). the adrf6620 is fabricated using an advanced silicon - germanium bicmos process. it is available in a 48 -lead , rohs -compliant, 7 mm 7 mm lfcsp package with an exposed pad. performance is specified over the ? 40 c to +85 c temperature range .
adrf6620 data sheet rev . 0 | page 2 of 52 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 rf input to if dga output system specifications ................. 3 synthesizer/pll specifications ................................................... 4 rf input to mixer output specifications .................................. 6 if dga specifications ................................................................. 7 digital log ic specifications ......................................................... 8 absolute maximum ratings ............................................................ 9 thermal resistance ...................................................................... 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 11 rf input to dga output system performance ..................... 11 phase - locked loop (pll) ......................................................... 13 rf input to mixe r output performance ................................. 17 if dga ........................................................................................ 20 spurious performance ................................................................ 22 theory of operation ...................................................................... 24 rf input switches ....................................................................... 24 tunable balun ............................................................................. 25 rf digita l step attenuator (dsa) ............................................ 25 active mixer ................................................................................ 25 digitally programmable variable gain amplifier (dga) .... 25 lo generation block ................................................................. 26 serial port interface (spi) ......................................................... 27 basic connections ...................................................................... 28 rf input balun insertion loss optimization ......................... 30 ip3 and noise figure optimization ......................................... 31 interstage filtering requirements ............................................ 35 if dga vs. load ......................................................................... 38 adc interfacing ......................................................................... 39 power modes ............................................................................... 40 layout .......................................................................................... 40 register map ................................................................................... 41 register address descriptions ...................................................... 42 register 0x00, reset: 0x00000, name: soft_reset ........... 42 register 0x01, reset: 0x8b7f, name: enables ........................ 42 register 0x02, reset: 0x0058, name: int_div ..................... 43 register 0x03, reset: 0x0250, name: frac_div ................. 43 register 0x04, reset: 0x0600, name: mod_div .................. 43 register 0x20, reset: 0x0c26, name: cp_ctl ...................... 44 register 0x2 1, reset: 0x0003, name: pfd_ctl .................... 45 register 0x22, reset: 0x000a, name: flo_ctl ................... 46 register 0x23, reset: 0x0000, name: dga_ctl ................... 47 register 0x30, reset: 0x00000, name: balun_ctl ............ 48 register 0x31, reset: 0x08ef, name: mixer_ctl .............. 48 register 0x40, reset: 0x0010, name: pfd_ctl2 .................. 49 register 0x42, reset: 0x000e, name: dith_ctl1 ............... 50 register 0x43, reset: 0x0001, name: dith_ctl2 ............... 50 outline dimensions ....................................................................... 51 ordering guide .......................................................................... 51 revision history 7/ 13 revision 0: initial version
data sheet adrf6620 rev. 0 | page 3 of 52 specifications vcc x = 5 v, t a = 25 c , unless otherwise noted . table 1 . parameter test conditions/comments min typ max unit lo input internal lo frequency range 350 2850 mhz external lo frequency range lo_div_a = 00 350 3200 mhz lo input level ?6 0 +6 dbm lo input impedance 50 rf input input frequency 700 2700 mhz input return loss 12 db input impedance 50 rf digital step at tenuator attenuation range step size = 1 db 0 15 db power supply 4.75 5.0 5.25 v power consumption lo output buffer disabled external lo + if dga enabled 1.3 w internal lo + if dga enabled 1.7 w only if dga enabled 0.6 w power - down current 6 ma rf input to if dga ou tput system specification s vcc x = 5 v, t a = 25 c, high -s ide lo injection, f if = 200 mhz, internal lo frequency, if dga output load = 150 ?, and 2 v p- p differential output with third - order low - pass filter, unless otherwise noted . for mixer settings for maximum linearity, see table 16 . all losses from input and output traces and baluns are de - embe dded from results table 2 . rf switch + balun + rf attenuator + mixer + if dga parameter test conditions/comments min typ max unit dynamic performance at f rf = 900 mhz f if = 200 mhz voltage conversion gain 12 db output p1d b 18 dbm o utput ip3 1 v p- p each output tone, 1 mhz tone spacing 43 dbm o utput ip2 1 v p -p each output tone, 1 mhz tone spacing 78 dbm noise figure noise figure optimized 16 db dynamic performance at f rf = 1900 mhz f if = 200 mhz voltage conversion gain 11 db output p1db 18 dbm output ip3 1 v p - p each output tone, 1 mhz tone spacing 45 dbm output ip2 1 v p - p each output tone, 1 mhz tone spacing 75 dbm noise figure noise figure optimized 18.5 db dynamic performance at f rf = 2100 mhz f if = 200 mhz db voltage conversion gain 10.5 dbm output p1db 18 dbm output ip3 1 v p - p each output tone, 1 mhz tone spacing 45 dbm output ip2 1 v p - p each output tone, 1 mhz tone spacing 66 dbm noise figure noise figure optimiz ed 19 db dynamic performance at f rf = 2700 mhz f if = 200 mhz voltage conversion gain 9 db output p1db 18 dbm output ip3 1 v p - p each output tone, 1 mhz tone spacing 44 dbm output ip2 1 v p - p each output tone, 1 mhz tone spacing 74 dbm noise figure noise figure optimized 21 db
adrf6620 data sheet rev . 0 | page 4 of 52 synthesizer/pll s pecifications vcc x = 5 v, t a = 25c, f ref = 153.6 mhz, f ref power = 4 dbm, f pfd = 38.4 mhz, and loop filter bandwidth = 12 0 k hz , unless otherwise noted. table 3 . param eter test conditions/comments min typ max unit pll reference pll reference frequency 12 464 mhz pll reference level for pll lock condition ? 15 +4 + 14 dbm pfd frequency 24 58 mhz internal vco range 2800 5700 mhz open - loop vco phase noise vt une = 2 v , lo_div_a = 00 f vco2 = 3.4 ghz 1 khz o ffset ? 39 dbc/hz 10 khz offset ? 81 dbc/hz 100 khz offset ? 103 dbc/hz 800 khz offset ? 123 dbc/hz 1 mhz offset ? 125 dbc/hz 6 mhz offset ? 143 dbc/hz 10 mhz offset ? 147 dbc/hz 40 mhz offset ? 155 dbc/hz vco s ensitivity (k v ) 88 mhz/v f vco1 = 4.6 ghz 1 khz offset ? 39 dbc/hz 10 khz offset ? 74 dbc/hz 100 khz offset ? 101 dbc/hz 800 khz offset ? 123 dbc/hz 1 mhz offset ? 125 dbc/hz 6 mhz offset ? 143 dbc/hz 10 mhz offset ? 147 dbc/hz 40 mhz offset ? 156 dbc/hz vco s ensitivity (k v ) 89 mhz/v f vco0 = 5.5 ghz 1 khz offset ? 39 dbc/hz 10 khz offset ? 69 dbc/hz 100 khz offset ? 99 dbc/hz 800 khz offset ? 121 dbc/hz 1 mhz offset ? 124 dbc/hz 6 m hz offset ? 142 dbc/hz 10 mhz offset ? 146 dbc/hz 40 mhz offset ? 155 dbc/hz vco s ensitivity (k v ) 72 mhz/v synthesizer specifications measured at lo output , lo_div_a = 01 f lo = 1.710 ghz, f vco2 = 3.420 ghz f ref = 1 53.6 mhz, f pfd = 38.4 mhz , 120 khz loop filter f pfd spurs f pfd 1 ? 83 dbc f pfd 2 ? 89 dbc f pfd 3 ? 90 dbc f pfd 4 ? 93 dbc closed - loop phase noise 1 khz offset ? 97 dbc/hz 10 khz offset ? 110 dbc/hz 100 khz offset ? 107 dbc/hz 800 khz offset ? 128 dbc/hz 1 mhz offset ? 132 dbc/hz 6 mhz offset ? 144 dbc/hz 10 mhz offset ? 152 dbc/hz 40 mhz offset ? 158 dbc/hz integrated phase noise 10 khz to 40 mhz integration bandwidth 0.21 rms figure of merit (fom) 1 ? 222 dbc/hz
data sheet adrf6620 rev. 0 | page 5 of 52 param eter test conditions/comments min typ max unit f lo = 2.305 g hz, f vco1 = 4.610 ghz f pfd spurs f pfd 1 ? 84 dbc f pfd 2 ? 87 dbc f pfd 3 ? 91 dbc f pfd 4 ? 92 dbc closed - loop phase noise 1 khz offset ? 93 dbc/hz 10 khz offset 105 dbc/hz 100 khz offset ? 103 dbc/hz 800 khz offset ? 116 dbc/hz 1 mhz offset ? 130 dbc/hz 6 mhz offset ? 144 dbc/hz 10 mhz offset ? 152 dbc/hz 40 mhz offset ? 156 dbc/hz in tegrated phase noise 10 khz to 40 mhz integration bandwidth 0.3 rms figure of merit 1 ? 222 dbc/hz f lo = 2.75 ghz, f vco2 = 5.5 ghz f pfd spurs f pfd 1 ? 82 dbc f pfd 2 ? 88 dbc f pfd 3 ? 93 dbc f pfd 4 ? 96 dbc closed - loop phase noise 1 khz offset ? 93 dbc/hz 10 khz offset ? 101 dbc/hz 100 khz offset ? 99 dbc/hz 800 khz offset ? 122 dbc/hz 1 mhz offset ? 128 dbc/hz 6 mhz offset ? 144 dbc/hz 10 mhz offset ? 151 dbc/hz 40 mhz offset ? 154 dbc/hz integrated phase noise 10 khz to 40 mhz integration bandwidth 0.38 rms figure of merit 1 ? 222 dbc/hz 1 f igure of merit (fom) is computed as phase noise (dbc/hz) C 10 l og 10(f pfd ) C 20 l og 10(f lo /f pfd ). the fom was measured across the full lo range, with f ref = 160 mhz and f ref power = 4 dbm (500 v/s slew rate) with a 40 mhz f pfd . the fom was computed at 50 k hz off s et .
adrf6620 data sheet rev. 0 | page 6 of 52 rf input to mixer output specifications vccx = 5 v, t a = 25c, high-side lo injection, f if = 200 mhz, external lo frequency, and rf attenuation = 0 db, unless otherwise noted. mixer settings configured for maximum linearity (see table 16). all losses from input and output traces and baluns are de-embed ded from results. table 4. rf switch + balu n + rf attenuator + mixer parameter test conditions/comments min typ max unit voltage gain differential 255 load ?4 db mixer output impedance differential (see figure 87 ) 255 dynamic performance at f rf = 900 mhz voltage conversion gain ?2 db input p1db 17 dbm input ip3 ?5 dbm each input tone, 1 mhz tone spacing 40 dbm input ip2 ?5 dbm each input tone, 1 mhz tone spacing 65 dbm noise figure 15 db lo to rf leakage ?70 dbm rf to lo leakage ?60 dbc lo to if leakage ?32 dbm rf to if leakage with respect to 0 dbm rf input power ?45 dbc isolation 1 isolation between rfin0 and rfin3 ?52 dbc dynamic performance at f rf =1900 mhz voltage conversion gain ?3 db input p1db 17 dbm input ip3 ?5 dbm each input tone, 1 mhz tone spacing 40 dbm input ip2 ?5 dbm each input tone, 1 mhz tone spacing 62 dbm noise figure 17 db lo to rf leakage ?60 dbm rf to lo leakage ?50 dbc lo to if leakage ?35 dbm rf to if leakage with respect to 0 dbm rf input power ?43 dbc isolation 1 isolation between rfin0 and rfin3 ?47 dbc dynamic performance at f rf = 2100 mhz voltage conversion gain ?3.5 db input p1db 18 dbm input ip3 ?5 dbm each input tone, 1 mhz tone spacing 40 dbm input ip2 ?5 dbm each input tone, 1 mhz tone spacing 54.5 dbm noise figure 18 db lo to rf leakage ?60 dbm rf to lo leakage ?40 dbc lo to if leakage ?35 dbm rf to if leakage with respect to 0 dbm rf input power ?40 dbc isolation 1 isolation between rfin0 and rfin3 ?45 dbc dynamic performance at f rf = 2700 mhz voltage conversion gain ?4.7 db input p1db 19 dbm input ip3 ?5 dbm each input tone, 1 mhz tone spacing 40 dbm input ip2 ?5 dbm each input tone, 1 mhz tone spacing 56 dbm noise figure 21 db lo to rf leakage ?60 dbm rf to lo leakage ?45 dbc lo to if leakage ?40 dbm rf to if leakage with respect to 0 dbm rf input power ?42 dbc isolation 1 isolation between rfin0 and rfin3 ?41 dbc 1 isolation between rf inputs. an input sign al was applied to rfin0 while rfin1 to r fin3 were terminated with 50 . the if signa l amplitude was measured at the mixer output. the internal switch was then conf igured for rfin3, and the feedthrough was measured as a delta from the fundamental.
data sheet adrf6620 rev. 0 | page 7 of 52 if dga specifications vcc x = 5 v, t a = 25 c, r s = r l = 150 ? differential , f if = 200 mh z, 2 v p - p differential output , unless otherwise noted . all losses from input and output traces and baluns are de - embedded from results . table 5 . parameter test conditions/comments min typ max unit bandwidth ? 1 db b andwidth v out = 2 v p -p 5 00 mhz ? 3 db b andwidth v out = 2 v p -p 700 mhz slew rate 5.5 v/ns input stage input p1db at minimum g ain 17 dbm input impedance 150 common - mode input voltage 1. 5 v c ommon - mode rejection ratio ( cmrr ) 50 db gain power /voltage gain , step s ize = 0.5 db 3 15 db gain flatness 50 mhz < f c < 200 mhz 0.2 db gain conformance error 0.1 db gain temperature sensitivity 0.008 db/c gain step response 15 ns output stage output p1db 18 dbm output impedance see figure 88 150 noise/harmonic performance at 200 mh z output ip3 1 v p - p each output tone, 1 mhz tone spacing 45 dbm output ip2 1 v p - p each output tone, 1 mhz tone spacing 63 dbm hd2 v out = 2 v p -p ? 87 dbc hd3 v out = 2 v p -p ? 84 dbc noise figure 10 db
adrf6620 data sheet rev . 0 | page 8 of 52 digital logic specif ications table 6 . parameter symbol test conditions/comments min typ max unit serial port interface timing input voltage high v ih 1.4 v input voltage low v il 0.70 v output voltage high v oh i oh = ?100 a 2.3 v output voltage low v ol i ol = +100 a 0.2 v serial clock period t sclk 38 ns setup time between data and rising edge of sclk t ds 8 ns hold time between data and rising edge of sclk t dh 8 ns setup time between falling edge o f cs and sclk t s 10 ns hold time between rising edge of cs and sclk t h 10 ns minimum period sclk can be in logic high state t high 10 ns minimum period sclk can be in logic low state t low 10 ns m aximum time delay between falling edge of sclk and output data valid for a read operation t access 231 ns maximum time delay between cs deactivation and sdio bus return to high impedance t z 5 ns timing diagram t s t ds t dh t high t low t sclk t h don't care don't care a5 a4 a3 a2 a1 a0 d15 d14 d13 d3 d2 d1 d0 don't care don't care sclk sdio r/w t z t access a6 1 1489-002 cs figure 2. serial port interface timing
data sheet adrf6620 rev. 0 | page 9 of 52 absolute maximum rat ings table 7. parameter rating vcc x ? 0.5 v to + 5.5 v rfsw0, rfsw1 ? 0.3 v to + 3.6 v rfin0, rfin1, rfin2, rfin3 20 dbm loin ? , loi n+ 16 dbm refin ? 0.3 v to + 3.6 v ifin ? , ifin+ ? 1.2 v to + 3.6 v cs , sclk, sdio ? 0.3 v to + 3.6 v vtune ? 0.3 v to + 3.6 v operating temperature range ? 40c to +85c storage temperature range ? 65c to + 150c maximum junction temperature 150c stresses abov e those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance table 8 . thermal resistance package type jc unit 48- lead lfcsp 1.62 c /w esd caution
adrf6620 data sheet rev . 0 | page 10 of 52 pin configuration and function descripti ons 13 14 15 16 17 18 19 20 21 22 23 24 vcc3 vcc4 ifin? ifin+ gnd mxout+ mxout? gnd loout+ loout? gnd vcc5 48 47 46 45 44 43 42 41 40 39 38 37 gnd vtune decl4 loin+ loin? muxout sdio sclk cs rfsw1 rfsw0 decl3 1 2 3 4 5 6 7 8 9 10 11 12 vcc1 decl1 cp gnd gnd refin decl2 ifout1+ ifout1? ifout2+ ifout2? vcc2 notes 1. the exposed p ad must be connected to a ground plane with low therma l impedance. rfin0 gnd gnd rfin1 gnd gnd rfin2 gnd gnd rfin3 gnd 35 gnd36 34 33 32 31 30 29 28 27 26 25 top view (not to scale) pin 1 indic at or adrf6620 1 1489-003 figure 3. pin configuration table 9 . pin function descriptions 1 pin no. mnemonic description 1, 12, 13, 14, 24 vcc1, vcc2, vcc3, vcc4, vcc5 5 v power supplies . decouple all power supply pins to ground, using 100 pf and 0.1 f capacitors. plac e the decoupling capacitors near the pins . 2, 7, 37, 46 decl1, decl2, decl3, decl4 decouple all declx pins t o ground, using 100 pf, 0.1 f, a nd 10 f capacitors. place the decoupling capacitors near the pin s. 3 cp synthesizer charge pump output. connect this pin to the vtune pin through the loop filter. 4, 5, 17, 20, 23, 25, 27, 28, 30, 31, 33, 34, 36, 48 gnd ground. 6 refin synthesizer reference frequency i nput . 8 to 11 ifout1+, ifout1?, ifout2+, ifout2? if dga outputs. connect the positive pins such that ifout1+ and ifout2+ are tied together. similarly, connect the negative pins such that ifout1? and ifou t2? are tied together. refer to the layout section for a recommended layout that minimizes parasitic capacitance and optimizes performance. 15, 16 ifin?, ifin+ differential if dga i nputs . ac couple the mixer outputs to the if dga inputs. 18, 19 mxout+, mxout? different ial mixer o utputs. ac couple the mixer outputs to the if dga inputs. 21, 22 loout+, loout? differential lo outputs. the differential output impedance is 50 . 26, 29, 32, 35 rfin3 , rfin2, rfin1, rfin0 rf input s . the se single - ended rf inputs have a 50 input impedance and must be ac - coupled . 38, 39 rfsw0, rfsw1 external pin control of rf input switch es . for logic high, connect these pin s to 2.5 v logic. 40 cs spi chip select, active low. 3.3 v tolerant logic levels. 41 sclk spi clock. 3.3 v tolerant logic levels. 42 sdio spi data input or output. 3.3 v tolerant logic levels. 43 muxout multiplexer output. this output pin provides the pll reference signal or the pll lock detect signal. 44, 45 loin?, loin+ differe ntial local oscillator inputs. the d ifferential input impedance is 50 . 47 vtune vco tuning voltage. connect this pin to the cp pin through the loop filter. 49 epad exposed pad. the exposed pad must be c onnect ed to a ground plane wit h low thermal impedance . 1 for more connection information about these pins, see table 14 .
data sheet adrf6620 rev. 0 | page 11 of 52 typical performance characteristics rf input to dga o utput system performance vcc x = 5 v, t a = 25 c, rfdsa _sel = 00 ( 0 db ), rfsw_sel = 0 0 (rfin0) , bal_cin and bal_cout optimized for max imum gain; mix er _bias, mix er _rdac , and mix er _cdac optimized for highest linearity, d ga at max imum gain; thi rd - order low - pass filter between the mixer output and if dga input; high - side lo, internal lo frequency, if f req uency = 200 mhz , unless otherwise noted . all losses from input and output traces and baluns are de - embedded from results . 5 6 7 8 9 10 11 12 13 14 15 600 1000 1400 1800 2200 2600 3000 gain (db) rf frequenc y (mhz) t a = ?40c t a = +85c t a = +25c 1 1489-004 figure 4. g ain vs. rf fre quency; if freq uency = 200 mhz 0 2 4 6 8 10 12 14 16 18 20 22 600 1000 1400 1800 2200 2600 3000 op1db (dbm) rf frequenc y (mhz) t a = ?40c t a = +85c t a = +25c 1 1489-005 figure 5. o p1db vs. rf frequency 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 50 100 150 200 250 300 350 400 450 500 gain (db) if frequenc y (mhz) rf frequenc y = 900mhz rf frequenc y = 2700mhz rf frequenc y = 2100mhz rf frequenc y = 1900mhz 1 1489-007 figure 6. gain vs. if frequency; lo sweep with fixed rf, if roll - off if frequenc y (mhz) 0 2 4 6 8 10 12 14 16 18 20 22 50 100 150 200 250 300 350 400 450 500 op1db (dbm) rf frequenc y = 900mhz rf frequenc y = 1900mhz rf frequenc y = 2100mhz rf frequenc y = 2700mhz 1 1489-008 figure 7. op1db vs. if frequency; lo sweep with fixed rf, if roll - off
adrf6620 data sheet rev . 0 | page 12 of 52 rf frequenc y (mhz) 5 15 25 35 45 55 65 75 85 95 600 1000 1400 1800 2200 2600 3000 oip2 (dbm), oip3 (dbm) t a = ?40c t a = +85c t a = +25c oip2 (dbm) oip3 (dbm) 1 1489-006 figure 8. oip2/oip3 vs. rf frequency; measured on 1 v p - p on each tone at dga outp ut 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 50 100 150 200 250 300 350 400 450 500 gain (db) if frequenc y (mhz) lo frequenc y = 1 100mhz lo frequenc y = 2300mhz lo frequenc y = 2100mhz 1 1489- 1 10 figure 9. gain vs. if frequency; rf sweep with fixed lo; if and rf roll - off ; measured on 1 v p - p on each tone at dga output 5 15 25 35 45 55 65 75 85 95 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 oip2 (dbm), oip3 (dbm) rfds a rf frequenc y = 900mhz rf frequenc y = 1900mhz rf frequenc y = 2100mhz rf frequenc y = 2700mhz oip2 (dbm) oip3 (dbm) 1 1489- 11 1 figure 10 . oip2/oip3 vs. rfdsa ; measured on 1 v p - p on each tone at dg a output if frequenc y (mhz) 5 15 25 35 45 55 65 75 85 95 50 100 150 200 250 300 350 400 450 500 oip2 (dbm), oip3 (dbm) rf frequenc y = 900mhz rf frequenc y = 1900mhz rf frequenc y = 2100mhz rf frequenc y = 2700mhz oip3 (dbm) oip2 (dbm ) 1 1489-009 figure 11 . oip2/oip3 vs. if frequency; lo sweep with fixed rf, if roll - off; measured on 1 v p - p on each tone at dga output oip3 (dbm) oip2 (dbm) if frequenc y (mhz) 5 15 25 35 45 55 65 75 85 95 50 100 150 200 250 300 350 400 450 500 oip2 (dbm), oip3 (dbm) lo frequenc y = 1 100mhz lo frequenc y = 2300mhz lo frequenc y = 2100mhz 1 1489- 1 12 figure 12 . oip2/oip3 vs. if frequency; rf sweep with fixed lo; i f an d rf roll - off ; measured on 1 v p - p on each tone at dga output 0 50 100 150 200 250 300 350 400 450 500 600 1000 1400 1800 2200 2600 3000 supply current (ma) rf frequenc y (mhz) t a = ?40c t a = +85c t a = +25c 1 1489- 1 13 figure 13 . supply current vs. rf frequency
data sheet adrf6620 rev. 0 | page 13 of 52 phase - locked loop (pll) vcc x = 5 v, t a = 25 c, 120 khz loop f ilter, f ref = 153.6 mhz, pll reference a mplitude = 4 dbm, f pfd = 38.4 mhz , measured at lo o utput, unless otherwise noted . ?160 ?150 ?140 ?130 ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) offset frequenc y (hz) 1 1489-010 figure 14 . vco 2 open - loop vco phase noise vs. offset frequency ; f vco 2 = 3.4 ghz, lo _ div _a = 00 , vtune = 2 v ?160 ?150 ?140 ?130 ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) offset frequenc y (hz) 1 1489-0 11 figure 15 . vco 1 open - loop phase noise vs. offset frequency; f vco 1 = 4.6 ghz, lo_div_a = 0 0 , vtune = 2 v ?160 ?150 ?140 ?130 ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) offset frequenc y (hz) 1 1489-012 figure 16 . vco 0 open - loop phase noise vs. offset frequency; f vco 0 = 5.5 ghz, lo_div_a = 0 0 , vtune = 2 v 1k 10k 100k 1m 10m 100m offset frequenc y (h z) ?160 ?155 ?150 ?145 ?140 ?135 ?130 ?125 ?120 ?1 15 ?1 10 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 phase noise (dbc/hz) lo_div_ a = 00 lo_div_ a = 01 lo_div_ a = 10 lo_div_ a = 11 1 1489-013 figure 17 . vco 2 closed - loop phase noise for various lo_div_a d ividers vs. offset frequency; f vco2 = 3.4 ghz 1k 10k 100k 1m 10m 100m offset frequenc y (hz) ?160 ?155 ?150 ?145 ?140 ?135 ?130 ?125 ?120 ?1 15 ?1 10 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 phase noise (dbc/hz) lo_div_ a = 00 lo_div_ a = 01 lo_div_ a = 10 lo_div_ a = 11 1 1489-014 figure 18 . vco 1 closed - loop phase noise for various lo_div_a d ividers vs. offset frequency; f vco1 = 4.6 ghz 1k 10k 100k 1m 10m 100m offset frequenc y (hz) ?160 ?155 ?150 ?145 ?140 ?135 ?130 ?125 ?120 ?1 15 ?1 10 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 phase noise (dbc/hz) lo_div_ a = 00 lo_div_ a = 01 lo_div_ a = 10 lo_div_ a = 11 1 1489-015 figure 19 . vco 0 closed - loop phase noise for various lo_div_a d ividers vs. offset frequency; f vco0 = 5.532 ghz
adrf6620 data sheet rev. 0 | page 14 of 52 230 225 220 215 210 205 200 1400 1600 1800 2000 2200 2400 2600 2800 fom (dbc/hz/hz) lo frequenc y (mhz) 1 1489-016 t a = ?40c t a = +25c t a = +85c figure 20 . pll figure of merit (fom) vs. lo frequency ?160 ?150 ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 phase noise (dbc/hz) vco frequency (mhz) t a = ?40c t a = +25c t a = +85c 1khz offset 10khz offset 100khz offset 800khz offset 6mhz offset 1 1489-017 2579 2979 3379 3779 4179 4579 4979 5379 5779 figure 21 . open - loop phase noise vs. vco frequency ; lo_div_a = 00 1 1489-018 ?160 ?155 ?150 ?95 ?145 ?140 ?135 ?130 ?125 ?120 ?1 15 ?1 10 ?105 ?100 ?90 ?85 phase noise (dbc/hz) lo frequenc y (mhz) 1384 1584 1784 1984 2184 2384 2584 2784 t a = ?40c t a = +25c t a = +85c 1khz offset 50khz offset 400khz offset 1mhz offset 10mhz offset ?165 figure 22 . 120 khz bandwidth loop phase noise , lo_div_a = 0 1; offset = 1 k hz, 50 khz, 400 k hz, 1 mhz, and 10 mhz 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 2800 3200 3600 4000 4400 4800 5200 5600 v tune (v) vco frequency (mhz) t a = ?40c t a = +25c t a = +85c 1 1489-019 figure 23 . v tune vs. vco frequency ?160 ?155 ?150 ?145 ?140 ?135 ?130 ?125 ?120 ? 1 15 ? 1 10 ?105 ?100 2579 2979 3379 3779 4179 4579 4979 5379 5779 phase noise (dbc/hz) vco frequency (mhz) t a = ?40c t a = +25c t a = +85c 1mhz offset 10mhz offset 40mhz offset 1 1489-020 figu re 24 . open - loop phase noise vs. vco frequency ; lo_div_a = 00 lo frequenc y (mhz) ?165 ?160 ?155 ?150 ?145 ?140 ?135 ?130 ?125 ?120 ?1 15 ?1 10 ?105 ?100 ?95 ?90 ?85 1384 1584 1784 1984 2184 2384 2584 2784 phase noise (dbc/hz) t a = ?40c t a = +25c t a = +85c 100khz offset 800khz offset 6mhz offset 40mhz offset 1 1489-021 figure 25 . 120 khz bandwidth loop phase noise, lo_div_a = 0 1; offset = 100 khz, 800 k hz, 6 mhz, and 40 mhz
data sheet adrf6620 rev. 0 | page 15 of 52 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 2768 5568 integr a ted phase noise, with spur ( rms) vco frequenc y (mhz) lo_div_ a = 01 lo_div_ a = 11 lo_div_ a = 10 t a = ?40c t a = +25c t a = +85c 1 1489-126 3168 3568 3968 4368 4768 5168 figure 26 . 10 khz to 40 mhz integrated phase noise vs. vc o frequency; lo_div_a = 01, 10 , and 11, i ncluding s purs , for various lo divider r atios ?1 10 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 2768 3168 3568 3968 4368 4768 5168 5568 vco frequency (mhz) reference spurs (dbc), 1 pfd offset t a = ?40c t a = +25c t a = +85c lo_div_ a = 01 lo_div_ a = 10 lo_div_ a = 11 1 1489-028 figure 27 . f pfd spurs vs. vco frequency; 1 pfd offset; measured at lo output ?1 10 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 2768 3168 3568 3968 4368 4768 5168 5568 vco f requenc y (mh z) reference spurs (dbc), 3 pfd offset t a = ?40c t a = +25c t a = +85c lo_div_ a = 01 lo_div_ a = 10 lo_div_ a = 11 1 1489-029 figure 28 . f pfd spurs vs. vco frequency; 3 pfd offset; measured at lo output 2768 5568 3168 3568 3968 4368 4768 5168 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 integr a ted phase noise, without spur ( rms) vco frequenc y (mhz) lo_div_ a = 01 lo_div_ a = 11 lo_div_ a = 10 t a = ?40c t a = +25c t a = +85c 1 1489-128 figure 29 . 10 khz to 40 mhz integrated phase noise vs. vc o frequency; lo_div_a = 01, 10 , and 11, excluding spurs, for various lo divider r atios ?1 10 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 2768 3168 3568 3968 4368 4768 5168 5568 vco frequenc y (mhz) reference spurs (dbc), 2 pfd offset t a = ?40c t a = +25c t a = +85c lo_div_ a = 01 lo_div_ a = 10 lo_div_ a = 11 1 1489-031 figure 30 . f pfd spurs vs. vco frequency; 2 pfd offset; measured at lo output vco frequency (mhz) 2768 3168 3568 3968 4368 4768 5168 5568 ?120 ?1 15 ?1 10 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 reference spurs (dbc), 4 pfd offset t a = ?40c t a = +25c t a = +85c lo_div_ a = 01 lo_div_ a = 10 lo_div_ a = 11 1 1489-032 figure 31 . f pfd spurs vs. vco frequency; 4 pfd offset; measured at lo output
adrf6620 data sheet rev. 0 | page 16 of 52 200 210 220 230 240 250 260 270 280 290 300 350 850 1350 1850 2350 2850 supply current (ma) lo frequenc y (mhz) lo_d rv_lvl = 00 lo_d rv_lvl = 01 lo_d rv_lvl = 10 lo_d rv_lvl = 11 t a = ?40c t a = +25c t a = +85c 1 1489-132 figure 32 . supply current vs. lo f requency ; lo_drv_lv l = 00, 0 1, 10 , and 11 rf frequenc y (mhz) ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 600 1000 1400 1800 2200 2600 3000 rf t o lo feedthrough (dbc) 1 1489-136 figure 33 . rf to lo output feedthrough, lo_drv_lv l = 0 0 2818.2 2823.2 2828.2 2833.2 2838.2 2843.2 2848.2 2853.2 2858.2 2863.2 2868.2 0 25 50 75 100 125 150 175 200 225 250 lo frequenc y (mhz) time (s) 1 1489-137 figure 34 . lo frequency settling time , loop filter bandwidth = 120 khz ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 350 850 1350 1850 2350 2850 lo amplitude (dbm) lo frequenc y (mhz) t a = ?40c t a = +25c t a = +85c lo_d rv_lvl = 00 lo_d rv_lvl = 01 lo_d rv_lvl = 11 lo_d rv_lvl = 10 1 1489-135 figure 35 . lo amplitude vs. lo frequency; lo_drv_lv l = 00 , 01, 10 , and 11 lo frequenc y (mhz) ?100 ?98 ?96 ?94 ?92 ?90 ?88 ?86 ?84 ?82 ?80 ?78 ?76 ?74 ?72 ?70 1384 1584 1784 1984 2184 2384 2584 2784 reference spurs (dbc), 1 pfd offset lo output dg a output 1 1489-023 figure 36 . f pfd spurs, lo_div_a = 01 , 1 pfd offset; measured on lo output and dga output
data sheet adrf6620 rev. 0 | page 17 of 52 rf input to mixer output performance vcc x = 5 v, t a = 25c, r l = 250 , external lo , p lo = 0 dbm, rfdsa _sel = 00 ( 0 db ), rfsw _ sel = 00 (rfin0) , bal_cin and bal_cout o ptimized, mix er _bias, mix er _rdac , and mix er _cdac optimized for highest linearity , dga and lo output disable d, unless otherwise noted . all losses from input and output traces and baluns are de - embedded from results . ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 600 1000 1400 1800 2200 2600 3000 gain (db) rf frequenc y (mhz) +85c +25c ?40c 1 1489-034 figure 37 . mixer gain vs. rf frequency 0 2 4 6 8 10 12 14 16 18 20 22 600 1000 1400 1800 2200 2600 3000 ip1db (dbm) rf frequenc y (mhz) 1 1489-035 t a = ?40c t a = +25c t a = +85c figure 38 . mixer i p1db vs. rf frequency rf frequenc y (mhz) 0 10 20 30 40 50 60 70 80 90 100 600 1000 1400 1800 2200 2600 3000 iip2 (dbm), iip3 (dbm) iip3 (dbm) iip2 (dbm) 1 1489-036 t a = ?40c t a = +25c t a = +85c figure 39 . mixer i ip2/ i ip3 vs. rf frequency; p in = ?5 dbm/ t one, 1 mhz s pacing if frequenc y (mhz) ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 0 100 200 300 400 500 600 700 800 900 1000 gain (db) rf frequenc y = 900mhz rf frequenc y = 1900mhz rf frequenc y = 2100mhz rf frequenc y = 2700mhz 1 1489-037 figure 40 . mixer gain vs. if frequency ; lo sweep with fixed rf, if roll -o ff if frequenc y (mhz) 0 100 200 300 400 500 600 700 800 900 1000 0 2 4 6 8 10 12 14 16 18 20 22 ip1db (dbm) rf frequenc y = 900mhz rf frequenc y = 1900mhz rf frequenc y = 2100mhz rf frequenc y = 2700mhz 1 1489-038 figure 41 . mixer i p1db vs. if frequency ; lo sweep with fixed rf, if roll - off 0 10 20 30 40 50 60 70 80 90 100 0 100 200 300 400 500 600 700 800 900 1000 iip2 (dbm), iip3 (dbm) if frequenc y (mhz) rf frequenc y = 900mhz rf frequenc y = 1900mhz rf frequenc y = 2100mhz rf frequenc y = 2700mhz iip2 (dbm) iip3 (dbm) 1 1489-039 figure 42 . mixer i ip2/ i ip3 vs. if frequency; p in = ?5 dbm/tone , 1 mhz s pacing , lo sweep with fi xed rf, if roll - off
adrf6620 data sheet rev. 0 | page 18 of 52 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 600 1000 1400 1800 2200 2600 3000 gain (db) rf frequenc y (mhz) rfsw_se l = 00 rfsw_se l = 01 rfsw_se l = 10 rfsw_se l = 11 1 1489-140 figure 43 . mixer gain vs. rf frequency ; rfsw _ sel = 0 0, 01, 10 , and 11 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 600 1000 1400 1800 2200 2600 3000 isol a tion (dbc) rf frequenc y (mhz) isol a tion rfsw_se l = 00 to 11 isol a tion rfsw_se l = 00 t o 01 isol a tion rfsw_se l = 00 t o 10 1 1489-142 figure 44 . mixer input to mixer output isolation vs. rf frequency; rfsw_sel = 00 driven ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 600 1000 1400 1800 2200 2600 3000 isol a tion (dbc) rf frequenc y (mhz) isol a tion rfsw_se l = 01 to 11 isol a tion rfsw_se l = 01 t o 00 isol a tion rfsw_se l = 01 t o 10 1 1489-141 figure 45 . mixer input to mixer output isolation vs. rf frequency ; rfsw _ sel = 01 driven rf frequenc y (mhz) 0 10 20 30 40 50 60 70 80 90 100 600 1000 1400 1800 2200 2600 3000 iip2 (dbm), iip3 (dbm) rfsw_se l = 00 rfsw_se l = 01 rfsw_se l = 10 rfsw_se l = 11 iip2 (dbm) iip3 (dbm) 1 1489-143 figure 46 . mixer i ip2/iip3 vs. rf frequency ; rfsw _ sel = 00, 01, 10, and 11 rf frequenc y (mhz) ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 600 1000 1400 1800 2200 2600 3000 isol a tion (dbc) isol a tion rfsw_se l = 11 to 11 isol a tion rfsw_se l = 11 t o 00 isol a tion rfsw_se l = 11 t o 01 1 1489-145 figure 47 . mixer input to mixer output isolation vs. rf frequency; rfsw_sel = 11 driven rf frequenc y (mhz) ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 600 1000 1400 1800 2200 2600 3000 isol a tion (dbc) isol a tion rfsw_se l = 10 to 11 isol a tion rfsw_se l = 10 t o 00 isol a tion rfsw_se l = 10 t o 01 1 1489-144 figure 48 . mixer input to mixer output isolation vs. rf frequency ; rfsw _ sel = 10 driven
data sheet adrf6620 rev. 0 | page 19 of 52 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 800 1200 1600 2000 2400 2800 3200 lo t o if feedthrough (dbm) lo frequenc y (mhz) 1 1489-146 figure 49 . lo to if feedthrough at mixer output without f iltering 800 1200 1600 2000 2400 2800 3200 rf frequenc y (mhz) ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 rf t o if feedthrough (dbc) 1 1489-147 figure 50 . rf to if feedthrough at mixer output without filtering; mixer input power = 0 dbm ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 350 600 850 1 100 1350 1600 1850 2100 2350 2600 2850 lo t o rf feedthrough (dbm) lo frequenc y (mhz) external lo interna l lo 1 1489-148 figure 51 . lo to rf feed through; p lo = 0 dbm 0 25 50 75 100 125 150 175 200 225 250 275 300 600 1000 1400 1800 2200 2600 3000 i cc (ma) rf frequenc y (mhz) t a = ?40c t a = +25c t a = +85c interna l lo external lo 1 1489-149 figure 52 . i cc vs. r f frequency; dga and lo output d isabled 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 600 1000 1400 1800 2200 2600 ssb noise figure (db) rf frequenc y (mhz) optimized for high linearit y noise figure optimized 1 1489-150 figure 53 . ssb noise figure vs. rf frequency (see table 16 )
adrf6620 data sheet rev. 0 | page 20 of 52 if dga vcc x = 5 v, t a = 25c, r s = r l = 150 , if = 200 mhz, 2 v p - p differential output, unless otherwise noted. all losses from input and output traces and baluns are de - embedded from results . 17 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 14 50 100 150 200 250 300 350 400 450 500 gain (db) if frequency (mhz) t a = ?40c t a = +25c t a = +85c gain = 15db gain = 11db gain = 7db gain = 3db 1 1489-151 figure 54 . dga gain vs. if frequency and temperature 20 18 16 14 12 10 8 6 4 2 0 50 100 150 200 250 300 350 400 450 500 op1db (db) if frequency (mhz) t a = ?40c t a = +25c t a = +85c 1 1489-152 figure 55 . dga op1db vs. frequency and temperature; maximum gain 80 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 50 100 150 200 250 300 350 400 450 500 oip2 (dbm), oip3 (dbm) if frequency (mhz) t a = ?40c t a = +25c t a = +85c oip2 (dbm) oip3 (dbm) 1 1489-153 figure 56 . dga oip2/oip3 vs. if frequenc y and temperature ; maximum gain ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 3 4 5 6 7 8 9 10 11 12 13 14 15 gain ste p error (db) gain (db) gain (db) t a = ?40c t a = +25c t a = +85c 1 1489-259 figu re 57 . dga gain and gain step error vs. gain setting and temperature 20 18 16 14 12 10 8 6 4 2 0 3 4 5 6 7 8 9 10 11 12 13 14 15 op1db (db) gain (db) t a = ?40c t a = +25c t a = +85c 1 1489-155 figure 58 . dga op1db vs. gain setting and temperature 3 4 5 6 7 8 9 10 11 12 13 14 15 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 oip2 (dbm), oip3 (dbm) gain (db) t a = ?40c t a = +25c t a = +85c oip2 (dbm) oip3 (dbm) 1 1489-156 figure 59 . dga oip2/oip3 vs. gain setting and temp erature
data sheet adrf6620 rev. 0 | page 21 of 52 50 500450400350300250200150100 ?50 ?70 ?60 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 0 ?20 ?10 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 hd2 (dbc) hd3 (dbc) if frequency (mhz) t a = ?40c t a = +25c t a = +85c 1 1489-157 figure 60 . dga hd2 /hd3 vs. if frequency and temperature; maximum gain ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 7 8 9 10 ?50 ?70 ?60 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 0 ?20 ?10 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 hd2 (dbc) hd3 (dbc) p out (dbm) gain = 3db gain = 7db gain = 11db gain = 15db 1 1489-158 figure 61 . dga hd2 /hd3 vs . output power (p out ) and gain setting 50 500450400350300250200150100 0 ?20 ?10 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 imd2 (dbc), imd3 (dbc) if frequency (mhz) t a = ?40c t a = +25c t a = +85c imd2 (dbc) imd3 (dbc) 1 1489-159 figure 62 . dga imd2/imd3 vs . if frequency and temperature; maximum gain 3 4 5 6 7 8 9 10 11 12 13 14 15 gain (db) ?50 ?70 ?60 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 0 ?20 ?10 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 hd2 (dbc) hd3 (dbc) t a = ?40c t a = +25c t a = +85c 1 1489-160 figure 63 . dga hd2/hd3 vs . gain setting and temperature ?7 ?6 ?5 ?4 ?3 ?5 ?1 0 1 2 3 4 5 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 oip2 (dbm), oip3 (dbm) p out (dbm) oip2 (dbm) oip3 (dbm) gain = 3db gain = 7db gain = 11db gain = 15db 1 1489-161 figure 64 . dga oip2/oip3 vs . output power (p out ) and gain setting 3 4 5 6 7 8 9 10 11 12 13 14 15 0 ?20 ?10 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 imd2 (dbc), imd3 (dbc) gain (db) t a = ?40c t a = +25c t a = +85c imd2 (dbc) imd3 (dbc) 1 1489-162 figure 65 . dga imd2/imd3 vs . gain setting
adrf6620 data sheet rev. 0 | page 22 of 52 spurious performance (n f rf ) ? (m f lo ) spur measurements were made using the s tandard evaluation board. mixer spurious products were measured in decibels ( db ) relative to the carrier (dbc) f rom the if outp ut power level. data is shown for a ll spurious components greater than ? 115 dbc and frequencies of less than 3 ghz. 9 15 mhz p erformance vcc x = 5 v, t a = 25c, rf power = 0 dbm, internal lo , f rf = 914 mhz, f lo = 1114 mhz m 0 1 2 3 4 5 6 n 0 ? 34 ? 35 1 ? 43 0 ? 52 ? 16 2 ? 72 ? 60 ? 72 ? 67 ? 74 3 ? 102 ? 73 ? 103 ? 78 data sheet adrf6620 rev. 0 | page 23 of 52 2700 mhz p erformance vcc x = 5 v, t a = 25c, rf power = 0 dbm, internal lo, f rf = 2700 mhz, f lo = 2500 mhz . m 0 1 2 3 4 5 6 n 0 ? 38.613 1 ? 40.126 ? 0.001 ? 43.84 2 ? 58.299 ? 67.06 ? 62.116 3 ? 73.603 adrf6620 data sheet rev. 0 | page 24 of 52 t heory of operation the adrf6620 integrates the essenti al elements of a multi - channel loopback receiver that is typically used in di gital predistortion systems . the main f eatures of the adrf6620 include a single - pole four throw (sp4t) rf input switch with tunable balun , variable attenuation , a wideband active mixer , and d igitally programmable variable gain amplifier (dga). in addition , the adrf6620 integrates a local oscillator (lo) generation block consisting of a synthesizer and a multicore voltage controlled oscillator ( vco ) with an octave range and low phase noise. the synthesizer uses a f ractional - n phase - lo cked loop ( pll ) to enable continuous lo coverage from 350 mhz to 285 0 mhz. putting all the building blocks of the adrf6620 together, the signal path thr ough the device starts at the rf input , where one of four single- ended rf inputs is selected by the input mux and converted to a differential signal via a tunable balun. the differential rf signal is attenuated to an optimal input level via the digital step attenuator with 15 db of attenuation range in steps of 1 db. the rf signal is then mixed via a gilbert cell mixer with the lo signal d own to an if frequency. the 255 terminated differen tial output of the mixer is brought off chip to a pair of inductors and passed through an if filter. the output of the if f ilter is ac - coupled off chip and fed to an on - chip digital attenuator and if dga . the output of the if dga is then passed to an off -c hip analog - to - digital converter ( adc ). rf input switches the adrf6620 integrates a sp4t switch where one of four rf inputs is selected. the desired rf input can be selected using either pin control or register writes via the spi . c ompared to the serial write approach, pin control allows faster control over the switch. when the rfsw0 pin ( pin 38 ) and the rfsw1 pin ( pin 39 ) are used , the rf switches can switch at speeds of up to 100 ns. when se rial port control is used , the switch time is 100 ns , plus the latency of the spi programming. the r fsw_mux bit (register 0x23, bit 11 ) selects whether the rf input switch is controlled via the external pins or the spi port . by default at power - up, the dev ice is configured for serial control. writing to the rfsw_sel bits ( register 0x23 , bits[10:9] ) allows selection of one of the four rf inputs. alternatively, by setting the rfsw_mux bit high, the rfsw0 and rfsw1 pins can be used to select the rf input. table 10 summarizes the different control options for the rf inputs. to maintain good channel - to - channel isolation, ensure that unused rf inputs are properly terminated . the rfin x ports are internally termin ated with 50 ? resistors and have a dc bias level of 2.5 v. to avoid disrupting the dc level, the recommended termination is a dc blocking capacitor to gnd. figure 66 shows the recom - mended configuration when only rfin0 is used , and the other rf input ports are properly terminated. rfin0 rfin1 rfin2 rfin3 0.1 f 0.1 f 0.1 f 50 50 50 50 1 1489-168 35 32 29 26 figure 66 . terminating unused rf input ports table 10 . rf input selection table rfsw_mux ( register address 0x23 [11] ) spi control , rfsw_sel ( registe r address 0x23 [10:9] ) pin control bit 11 bit 10 bit 9 rfsw1, pin 39 rfsw0, pin 38 rf input 0 0 0 x 1 x 1 rfin0 0 0 1 x 1 x 1 rfin1 0 1 0 x 1 x 1 rfin2 0 1 1 x 1 x 1 rfin3 1 x 1 x 1 0 0 rfin0 1 x 1 x 1 0 1 rfin1 1 x 1 x 1 1 0 rfin2 1 x 1 x 1 1 1 rfin3 1 x = dont care.
data sheet adrf6620 rev. 0 | page 25 of 52 tunable balun the adrf6620 integrates a programmable balun operating over a frequ ency range from 700 mhz to 2700 mhz. the tunable balun offers the ben efit of ease of drivability from a single - ended 50 rf inp ut , and the single - ended - to - differential conversion of the balun optimizes common - mode rejection. 1 1489-040 bal_cout reg 0x30[7:5] bal_cin reg 0x30[3:1] rfinx figure 67 . integrated tunable balun the rf balun is tuned by switching parallel capacitances on the primary and secondary sides by writing to register 0x30. the added capacitance , in parallel with the inductive windings of the balun , changes the resonant frequency of the inductive capacitive (lc) tank. therefore, selecting the proper combination of bal_ cin (register 0x30, bits[3:1]) and bal_cout (register 0x30, bits[7:5]) sets the desired frequency and minimizes the insertion loss of the balun . under most circumstances, the input and output can be tuned together; however, sometimes for matching reasons, it may be advantageous t o tune them separately. see the rf input balun insertion loss optimization section for the recommended bal_cin and bal_cout settings. rf digital step attenuator (dsa) the rf dsa follows the tunable balun . t he attenuation range is 0 db to 15 db with a step size of 1 db. dsa attenuation is set using the rfdsa_sel bits ( r egister 0x23 , bits [8:5] ). active mixer the double balanced mixer uses high performance sige npn transistors. this mixer is based on the gilbert cell design of four cross - connected transistors. the mixer output has a 255 differential output resistance. bias t he mixer outputs using either a pair of supply referenced rf chokes or an output transformer with the center tap connected to the positive supply. digitally p rogrammable variable gain a mplifier (dga) the adrf6620 integrates a differential if dga consisting of a 150 digitally controlled passive attenuator followed by a highly linear transconductance amplifier with feedback. the attenuation range is 12 db , and the transconductor amplifier has a fixed gain of 15 db . therefore, at minimum attenuation, the ga in of the if dga is 15 db; at maximum attenuation, the gain is 3 db. the attenuation is controlled by addressing the if_attn bits in register 0x2 3, bits[4:0]. the attenuation step size is 0.5 db. ref ifin+ ifin? ifout1+ ifout1? ifout2+ ifout2? a ttenu at or r in r s r out r l +5v g m am p logic 1 1489-041 15 16 11 8 9 10 figure 68 . simplified if dga schematic an independent internal voltage reference circuit sets the dc voltage level at the input of the amplifier to approximately 1.5 v. this ref erence is not accessible and cannot be adjusted. the if dga consumes 35 ma through the vcc 2 pin (pin 12) and 75 ma through the two output choke inductors . the if dga can be powered down by disabling the if_amp_en bit (r egister 0x01 , bit 11 ). in its power - down state , the if dga current reduces to 6 ma . the dc bias level at the input remains at approximately 1.5 v when the dga is disabled. at minimum attenuation , the gain of the if dga is 15 db when driving a 150 load. the source and load resistance of the amplifier is set to 150 in a matched condition. if the load or the source resistance is not equal to 150 , the following equation s can be used to determine the resulting gain and input/out put resistances. voltage gain = a v = 0.044 (1000|| r l ) r in = (1000 + r l )/(1 + 0.044 r l ) s21 ( gain ) = 2 r in /( r in + r s ) a v r out = (1000 + r s )/(1 + 0.044 r s ) the dc current to the outputs of each amplifier is supplied through two external choke induc tors . the inductance of the chokes and the resis tance of the load , in parallel with the output resistance of the device , add a low frequency pole to the response. the parasitic capacitance of the c h okes add s to the output capa - citance of the part. this tot al capacitance , in parallel with the load and output resistance , sets the high frequency pole of the device. in g eneral, the larger the inductance of the choke , the higher the parasitic capacitance. therefore, this trade - off must be considered when the value and type of the choke are selected. for each polarity, t he a mplifier has two output pins that are oriented in an alternating fashion : ifout1+ (pin 8), ifout1? (pin 9), ifout2+ (pin 10), and ifout2? (pin 11). when designing the board, minimize the parasitic capacitance caused by routing the corresponding outputs together . see the layout section for the recommended printed circu it board ( pcb ) layout.
adrf6620 data sheet rev. 0 | page 26 of 52 lo generation block the adrf6620 offers two modes for sourcing the lo signal to the mixer. the first mode uses the on - chip pll and vco . this mode of operation provides a high quality lo that meets the performance requirements of most applications. using the on - chip synthesizer and vco removes the burden of generating and distributing a high frequency lo signal. the second mode bypasses the integrated lo generation bloc k and allows the lo to be supplied externally. this second mode can provide a very high quality signal directly to the mixer core. sourcing the lo signal externally may be necessary in demanding applications that require the lowest possible phase noise per formance. external lo mode e xternal or internal lo mode can be selected via the vco_sel bits ( register 0x22, bits[2:0] ). to configure for external lo mode, set register 0x22 , bits [2:0] to 011 and apply the differential lo signals to p in 44 (loin ? ) and p in 45 (loi n+ ). the external lo fre quency range is 350 mhz to 3.2 ghz. t he adrf6620 offers the flexibility of using a higher lo frequency signal and di viding it down before it drives t he mixer. the lo divider can be found in the lo_div_a bits ( r egister 0x22 , bits [4:3] ) , where options include 1, 2, 4, or 8. the external lo input pins present a broadband differential 50 ? input impedance. the loin+ and loin? input pins must be ac - coup led. when not in use , loin+ and loin? can be left unconnected. internal lo mode the adrf6620 includes an on - chi p vco and pll for lo synthesis. the pll, shown in fi gure 69 , consists of a reference input , phase and frequency detector (pfd), charge pump, and a programmable integer divider with p rescaler. the reference path takes in a refe rence clock and divides it down by a factor of 1, 2, 4, or 8 or multiplies it by a factor of 2 before passing it to the pfd. the pfd compares this signal to the di vided down signal from the vco. depending on the pfd polarity selected, the pfd sends an up/down signal to the charge pump if the vco signal is slow/fast compared to the refe re nce frequency. the charge pump s ends a current pulse to the off - chip loop filter to increase or decrease the tuning voltage ( vtune ). the adrf6620 integrates three vco cores that cover an oc tave range from 2.8 ghz to 5.7 ghz. table 11 summarizes the fre - quency range for each vco. the desired vco can be selected by addressing the vco_sel bits ( r egister 0x22 , bits [2:0] ). table 11 . vco range vc o_sel ( register 0x22 , bits [2:0] ) frequency range (ghz) 000 5.2 to 5.7 00 1 4.1 to 5.2 010 2.8 to 4.1 011 external lo the n - divider divides down the differential vco signal to the pfd frequenc y. the n - divider can be configured for fractional mode or i nteger mode by addressing the div_mode bit ( r egister 0x02 , bit 11 ). the default configuration is set for fractional mode. + pfd charge pum p cp 2 n = int + frac mod 1, 2, 4, 8 loin? vtune external loo p fi lter lpf loin+ vco_se l reg 0x22[2:0] lo_div_ a reg 0x22[4:3] div_mode: reg 0x02[ 1 1] int_di v : reg 0x02[10:0] frac_di v : reg 0x03[10:0] mod_di v : reg 0x04[10:0] cp_ctr l reg 0x20[13:0] 1 2 8 4 2 refin refsel reg 0x21[2:0] pfd_polarity reg 0x21[3] loout+ t o mixer loout? t o mixer 1 1489-042 figure 69 . lo generation block diagram
data sheet adrf6620 rev. 0 | page 27 of 52 the following equations can be used to determine the n value a nd pll frequency : n f f vco pfd = 2 mod frac int n += lo_divider nf f pfd lo = 2 where: f pfd is the phase frequency detector frequency. f vco is the voltage controlled oscillator frequency. n is the fractional divide ratio (int + frac/mod) int is the integer divide ratio programmed in register 0x02. frac is the fractional divider programmed in register 0x03. mod is the modulus divide ratio programmed in register 0x04. f lo is the lo frequency going to the mixe r core when the loop is locked . lo_divider i s the final divider block that divides the vco fre quency down by 1, 2, 4, or 8 before it reaches the mixer (see table 12 ). this control is located in the lo_div_a bits (register 0x22, bits[4:3]). table 12. lo divider lo_div_a (register 0x22, bits[4:3]) lo_divider 00 1 01 2 10 4 11 8 the lock detect signal is available as one of the selectable outputs through the muxout pin; a logic high indicates that the loop is locked. t he muxout pin is controlled by the ref_mux_sel bits (register 0x21, bits[6:4]) ; the pll lock detec t signal is the default configuration. to ensure that the pll locks to the desired frequency, follow the proper write sequence of the pll registers. the pll registers must be configured acc ordingly to achieve the desired frequency, and the last writes must be to register 0x02 (int_div), register 0x03 (frac_div), or register 0x04 (mod_div). when one of the se registers is programmed, an internal vco calibration is initiated, which is the last step in locking the pll. the time it takes to lock the pll after the last register is written can be broken down into two parts: vco band calibration and loop settling. after the last register is written, the pll automatically performs a vco band calibrati on to choose the correct vco band. this calibration takes approximately 5120 pfd cycles. for a 40 mhz f pfd , this corresponds to 128 s. after calibration is complete, the feedback action of the pll causes the vco to eventually lock to the correct frequency . the speed with w hich this locking occurs depends on the non linear cycle - slipping behavior, as well as the small- signal settling of the loop. for an accurate estimation of the lock time, download the adisimp ll tool, which correctly captures th ese effects. in general, higher bandwidth loops tend to lock more quickly than lower bandwidth loop s. additional lo controls to access the lo signal going to the mixer core through the loo ut+ and loout? pins (pin 21 and pin 22) , enable the lo_d rv_ en bit in register 0x01, bit 7 . this setting offers direct monitoring of the lo signal to the mixer for debug purposes ; or the lo signal can be used to daisy - chain many devices synchro nously. one adrf6620 can serve as the master where the lo signal is sourced, and the subsequent slave devices share the same lo signal from the master. this flexibility substantially eases the lo require - ments of a system with multiple los. the lo output drive level is controlled by the lo_drv_lvl bits ( r egister 0x22 , bits [8:7] ). table 13 s hows the available drive levels. table 13 . lo drive level lo_drv_lvl ( register 0x22 , bits [8:7] ) amplitude (dbm) 00 ?4 01 0.5 10 3 11 4.5 serial port interfac e (spi) the spi port of t he adrf6620 allows the user to configure the device through a structured register space provided inside the chip . registers are accessed via the serial port interface and can be written to or read from via the serial port interface . the serial port interface consists of three control lines : sclk, sdio, and cs . sclk (serial clock) is the serial shift clock. the sclk signal clocks data on its rising edge . sdio (serial data input/o utput) is an input or output depending on the instruction being sent and the relative position in the timing frame. cs (chip select bar) is an active low control that gates the read and write cycles. the falling edge of cs , in conjunction with the rising edge of sclk , determines the start of the frame. all sclk a nd sdio activity is ignor ed when cs is high. table 6 and figure 2 show the serial timing and its definitions. the adrf6620 protocol consists of seven regist er address bits, followed by a r ead/ w rite indicator and 16 data bits. both the address and data fields are organized from msb to lsb. on a write cycle, up to 16 bits of serial write data are shifted in, msb to lsb. if the rising edge of cs occurs before the ls b of the serial data is latched , only the bits that were clocked in are written to the device. if more than 16 data bits are shifted in, the 16 most recent bits are written to the device . the adrf6620 input logic level for the write cycle supports a logic level as low as 1.8 v. on a read cycle, up to 1 6 bits of serial read data are shifted out, msb to lsb. data shifted out beyond 1 6 bits is undefined. it is not necessary for r ead back content at a given register address to correspond with the write data of the same address. the output logic level for a read cycle is 2.5 v.
adrf6620 data sheet rev. 0 | page 28 of 52 basic connections ifout1+ ifout1? ifout2+ ifout2? gnd spi inter f ace adrf6620 refin muxout vcc5 sdio sclk csb cs exposed p addle +5v +5v 470nh (0603) 470nh (0603) 39nh (0402) 39nh (0402) 0.1f (0402) 1h 1h 0.1f (0402) 100pf (0402) 0.1f (0402) 2.7nf (0603) 6.8pf (0402) 22pf (0402) 22pf (0402) 100pf (0402) 0? (0402) 0? (0402) 3k? (0402) 49.9? (0402) 0? (0402) 4 3 1 6 tc1-1-43a+ loout 100pf (0402) loout+ loout? 100pf (0402) 4 3 1 6 tc1-1-43a+ loin 4 3 2 1 6 loin vtune_t p open 100pf (0402) loin+ loin? vtune cp 100pf (0402) 100pf (0402) open (0402) ref_in rfin3 100pf (0402) rfin3 rfin1 100pf (0402) rfin1 rfin2 100pf (0402) rfin2 rfin0 100pf (0402) rfin0 muxout 10k? (0402) 10k? (0402) decl4 ifin? ifin+ mxout+ mxout? 42 41 40 4 5 17 20 23 25 27 28 30 31 33 34 36 48 18 19 15 16 9 8 11 10 21 22 45 44 47 3 14 13 12 46 37 7 2 1 24 10k? (0402) 10k? (0402) 6 26 32 29 35 38 39 43 rfsw0 s1 rfsw1 3.3v s2 3.3v 100pf (0402) 0.1f (0402) vcc4 100pf (0402) 0.1f (0402) vcc3 100pf (0402) 0.1f (0402) vcc2 100pf (0402) 0.1f (0402) vcc1 100pf (0402) 0.1f (0402) 10f (0603) 0.1f (0402) 100pf (0402) 10f (0603) 0.1f (0402) 100pf (0402) 100pf (0402) 0.1f (0402) 10f (0603) 100pf (0402) 0.1f (0402) 10f (0603) +5v red ldo vco ldo lo ldo 2.5v ldo 3.3v lock_det vp ta t charge pum p cp 8 4 2 1 2 + pfd loin? vtune loin+ 1, 2, 4, 8 2 n = int + frac mod dn p dn p tcm3-1t+ sclk sdio decl3 decl2 decl1 1 1489-043 dn p dn p figure 70 . bas ic connect ion diagram table 14. basic connections pin no. mnemonic description basic connection 5 v power 1 vcc1 lo, vco, mixer power supply decouple all power supply pins to ground using 100 pf and 0.1 f capacitors. place t he decoupling capacitors close to the pins. 12 vcc2 if dga power supply 13 vcc3 factory calibration pin 14 vcc4 factory calibration pin 24 vcc5 rf front - end power supply pll/vco 3 cp synthesizer charge pump output connect this pin to the vtun e pin through the loop filter . 6 refin synthesizer reference frequency input the nominal input level of this pin is 1 v p - p. the i nput range is 12 mhz to 464 mhz. this pin is internally biased and must be ac - coupled and t e rminated externally with a 50 r esistor. place the ac coupling capacitor b etween the pin and the resistor. when driven from an 50 rf signal generator, the recommended input level is 4 dbm . 21, 22 loout+, loout? differential lo output s the differential output impedance of these pins is 50 . the p ins
data sheet adrf6620 rev. 0 | page 29 of 52 pin no. mnemonic description basic connection are internally biased to 2.5 v and must be ac - coupled. 44, 45 loin?, loin+ differential lo input s the d ifferential input impedance of these pins is 50 . the p ins are internally biased to 2.5 v and must be ac - coupled. 43 muxout pll multip lex output this o utput pin provid es the pll reference signal or the pll lock detect signal . 47 vtune vco tuning voltage this pin is driven by the output of the loop filter ; its nominal input voltage range is 1.5 v to 2.5 v . rf inputs 26, 29, 32, 35 r fin3 , rfin2 rfin1 , rfin0 rf inputs the single - ended rf inputs have a 50 input impedance a nd are internally biased to 2.5 v. these pins must be ac - coupled . terminate unused rf inputs with a dc blocking capacitor to gnd to improve isolation. refer to the layout secti on for the recommended pcb layout for optimized channel - to - channel isolation . 38, 39 rfsw0, rfsw1 pin control of the rf inputs see table 10 f or the pin settings for rf input pin control . for logic high , connect these pins to 2.5 v logic. if dga 8, 9, 10, 11 ifout1+, ifout1?, ifout2+, ifout2? if dga output s the differential if dga outputs have two output pins for each polarity . t hey are ori ented in alternating fashion: ifout1+ ( p in 8), ifout1 ? (p in 9), ifout2+ ( p in 10) , and ifout2 ? (p in 11). connect t he posit ive pins s uch that ifout1+ and ifout2+ are tied together. similarly, connect the negative pins such that ifout1 ? and ifout2 ? are tied together. refer to the layout section for a recommended layout that minimizes parasitic capa citance and optimizes on performance. the output stage of the if dag is an open - collector configuration that requires a dc bias of 5 v . use bias choke inductors to achieve this configuration. c hoose the bias choke inductors s uch that they can handle a maxi mum current of 50 ma on each side. by design, the if dga is optimized for linearity when the source and load are terminated with 150 . 15, 16 ifin?, ifin+ if dga input s ac couple the mixer outputs to the if dga inputs. see the interstage filtering requirements section for the recommended filter designs. mixer outputs 18, 19 mxout+, mxout? differen tial mixer outputs the output stage of the mixer is an open collector configuration that requires a dc bias of 5 v. use b ias choke inductors to achieve this configuration. carefully choose t he bias choke inductors s uch that they can handle a maximum curren t of 50 ma on each side. the differential output impedance of the mixer is 255 . serial port interface 40 cs spi chip select active low. 3.3 v logic levels . 41 sclk spi clock 3.3 v tolerant logic levels . 42 sdio spi data input and output 3.3 v tolerant logic levels . ldo decoupling 2 decl1 3.3 v ldo decoupling decouple all declx pins to ground using 100 pf, 0.1 f, and 10 f capacitors . plac e the decoupling capacitors close to the pin. 7 decl2 2.5 v ldo decoupling 37 decl3 lo ldo decoupling 46 decl4 vco ldo decoupling gnd 4, 5, 17, 20 , 23, 25, 27, 28, 30, 31, 33, 34, 36, 48 gnd ground connect these pins to the gnd of the pcb. 49 (epad) exposed pad (epad) t he exposed thermal pad is on the bottom of the package. the exposed pad must be soldered to ground.
adrf6620 data sheet rev. 0 | page 30 of 52 rf input balun insertion l oss optimization as shown in figure 71 to figure 74, t he gain of the adrf6620 mixer has been characterized for every combination of bal _cin and bal_cout (register 0x30) . as shown , a range of bal_cin and bal_cout values can be used to optimize the gain of the adrf6620 . the optimized values do not change with temperature. afte r the values are chosen, the absolute gain changes over tem - perature; however, the signature of the bal_cin and bal_cout values is fixed. ?6 ?5 ?4 ?3 ?2 ?1 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 gain (db) bal_ cin/ bal_ cout bal_c out bal_c in ?40 c +25c +85c 1 1489-044 figure 71 . gain vs. bal_cin and bal_cout at rf = 900 mh z ?12 ?10 ?8 ?6 ?4 ?2 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 gain (db) bal_ cin/ bal_ cout ?40 c +25c +85c bal_c out bal_c in 1 1489-046 figure 72 . gain vs. bal_cin and bal_cout at rf = 2100 mhz at lower input frequencies, more capacitance is needed. this increase is achieved by programming higher codes into bal_cin and bal_cout. at high frequencies, less capacitance is required ; therefore , lower bal_cin and bal_cout codes are appropriate. table 16 provides a list of recomended bal_cin and bal_cout codes for popular radio frequencies. use figure 71 to figure 74 and table 16 only as guides ; do no t interpret them in the absolute sense because every application and pcb design varies. addi - tional fine - tuning may be necessary to achieve the maximum gain . ?10 ?9 ? 4 ? 5 ? 6 ? 7 ? 8 ? 3 ? 2 ? 1 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 gain (db) bal_ cin/ bal_ cout bal_c out bal_c in ?40 c +25c +85c 1 1489-045 figure 73 . gain vs. bal_cin and bal_cout at rf = 1900 mh z ?18 ?14 ?10 ?6 ?2 ?16 ?12 ?8 ?4 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 gain (db) bal_ cin/ bal_ cout bal_c out bal_c in ?40 c +25c +85c 1 1489-047 figure 74 . gain vs. bal_cin and bal_cout at rf = 2700 mhz
data sheet adrf6620 rev. 0 | page 31 of 52 ip3 and noise figure optimization the adrf6620 c an be co n figured for either improved per for - mance or reduced power consumption . in appli cations where performance is critical , the adrf6620 offers ip3 or noise figure optimization. however , i f power consumption is the priority , the mixer bias current can be reduced to save on the overall power at the expense of degraded performance . whatever the application specific needs are , the adrf6620 offers conf igurability that balances perfor mance and power consumption. adjustments to the mixer bias setting ha ve the most impact on p erformance and power . f or this reason , mixer bias sho uld be the first adjustment . the active mixer core of the adrf6620 is a linearized transconductor . with increased bias current , the transcon ductor becomes more linear , resulting in higher ip3 . the improved ip3 , however, i s at the expense of degrade d noise figure and increased power consum ption (see figure 75 ). for a 1- bit change of the mixer bias ( mixer_bias , reg ister 0x31 , bits [11:9]) , the current increases by 7.7 1 ma . 150 155 160 165 170 175 180 185 190 195 200 205 210 215 220 0 1 2 3 4 5 6 7 i cc (ma) mixer bias 900mhz 1900mhz 2100mhz 2600mhz rf freq: 1 7.71 m a 1 1489-057 figure 75. change in cu rren t consumption vs. mixer_bias inevitably, there is a limit on how much the bias current can increase before the improvement in linearity no longer justifies the increase in power and noise. the mixer core reaches a saturation point where further increases in bias current do not translate to improved performance. when that point is reached , it is best to decrease the bias current to a level where the desired performance is achieved. depending on the system specifications of the cus - tomer, a balance between l inearity , noise figure , and power can be a ttained . in addition to bias optimization, the adrf6620 also has configurable distortion cancellation circuitry . the linearized transconductor input of the adrf6620 is made up of a main path and a seco ndary path. through adjustments of the amplitude and p hase of the secondary path, the distorti on g enerated by the main path can be cancel ed, resulting in improved ip d 3 performance . the amplitude and phase adjustments are located in the following serial inter face bits: mixer_rdac (reg ister 0x31 , bits [8:5 ]) a nd mixer_cdac (reg ister 0x31 , bits [4:0]).
adrf6620 data sheet rev. 0 | page 32 of 52 figure 76 to figure 83 show the iip3 and noise figure sweep s fo r all mixer_ rdac, mixer_ cdac, and mixer_bias combi - nations. the iip3 vs. mixer_ rdac and mixer_ cdac figures show both a surface and a contour plot in one figure. the contour plot is located directly underneath the surface plot . the be st approach for reading the figure is to localiz e the peaks on the surface plot, w hich indicate maximum iip3 , and to follow the same color pattern to the contour plot to determine the optimized mixer_ rda c and mixer_ cdac value s. the overall shape of the iip3 plot does not vary with the mixer_bias setting ; therefore , only mixer_bias = 011 is displayed. 1 1489-093 0 5 10 15 0 5 10 15 20 25 30 35 40 mixer_rdac mixer_cdac iip3 (dbm) figure 76 . iip3 vs. mixer_rdac, mixer_cdac; mixer_ bias = 011 at rf frequency = 900 mhz 1 1489-094 0 5 10 15 0 5 10 15 20 25 30 35 40 mixer_cdac mixer_rdac iip3 (dbm) figure 77 . iip3 vs. mixer_rdac, mixer_cdac; mixer_bias = 011 at rf frequency = 1900 mhz the data shows that mixer_bias has the largest impact on performance. as previously mentioned and evident in the data, iip3 imp roves with increased mixer _bias, and noise figure is optimized at the lowest bias setting. taking a more detailed look at the data, the different mixer_ rdac and mixer_ cdac combinations can result in a ~5 db to + 10 db change in iip3 , but the noise figure ch anges by only ~0.5 db. these trends become very important in deciding the trade - offs between ip3, noise figure, and power consumption. the total current consumption of the adrf6620 does not c hange with mixer_ rdac and mixer_ cdac and varies only with the mixer bias settings (see figure 75 ). 15.0 15.5 16.0 16.5 17.0 17.5 18.0 18.5 19.0 19.5 noise figure (db) mixer_rdac mixer_cdac 900-0 900-2 900-4 900-6 900-7 mixer bias 0 1 2 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 3 4 5 7 8 10 11 13 14 6 9 12 15 1 1489-062 figure 78 . noise figure vs. mixer_rdac, mixer_cdac , and various mixer_bias values at rf frequency = 90 0 mhz mixer_rdac mixer_cdac 15.5 16.0 16.5 17.0 17.5 18.0 18.5 19.0 19.5 20.0 20.5 21.0 21.5 15.0 22.0 0 1 2 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 3 4 5 7 8 10 11 13 14 6 9 12 15 noise figure (db) 1900-0 1900-2 1900-4 1900-6 1900-7 mixer bias 1 1489-063 figure 79 . noise figure vs. mixer_rdac, mixer_cdac , and various mixer_bias values at rf frequency = 1900 mhz
data sheet adrf6620 rev. 0 | page 33 of 52 0 5 10 15 0 5 10 15 15 20 25 30 35 40 45 mixer_rdac mixer_cdac iip3 (dbm) 1 1489-060 figure 80 . iip3 vs. mixer_rdac, mixer_ cda c ; mixer_ bias = 011 at rf frequency = 21 00 mhz 0 5 10 15 0 10 20 15 20 25 30 35 40 45 iip3 (dbm) 1 1489-061 mixer_rdac mixer_cdac figure 81 . iip3 vs. mixer_rdac, mixer_ cdac; mixer_bias = 011 at rf frequency = 2700 mhz mixer_rdac mixer_cdac 15.5 16.0 16.5 17.0 17.5 18.0 18.5 19.0 19.5 20.0 20.5 21.0 21.5 22.0 22.5 23.0 15.0 23.5 0 1 2 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 3 4 5 7 8 10 11 13 14 6 9 12 15 noise figure (db) 2100-0 2100-2 2100-4 2100-6 2100-7 mixer bias 1 1489-064 figure 82 . noise figure vs. mixer_rdac, mixer_cdac, and various mixer_bias values at rf frequency = 2100 mhz mixer_rdac mixer_cdac 0 1 2 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 3 4 5 7 8 10 11 13 14 6 9 12 15 noise figure (db) 2600-0 2600-2 2600-4 2600-6 2600-7 mixer bias 15.0 15.5 16.0 16.5 17.0 17.5 18.0 18.5 19.0 19.5 20.0 20.5 21.0 21.5 22.0 22.5 23.0 23.5 24.0 24.5 25.0 25.5 26.0 26.5 1 1489-065 figure 83 . noise figure vs. mixer_rdac, mixer_cdac, and various mixer_bias values at rf frequency = 2700 mhz
adrf6620 data sheet rev. 0 | page 34 of 52 as an example, the mixer_ rdac, mixer_ cdac, and mixer_ bias settings of the adrf6620 were carefully selected , based on t hr ee individual goals that resulted in three sets of mixer_ r dac, mixer_ c dac, and mixer_bias values. the first goal was for optimized iip3. to achieve the most optimal iip3 p erformance, the mixer_bias was set to a higher current setting, and mixer_ r dac and mixer_ c dac were selected at the peaks. this configuration allowed for the most optimal iip3 performance. h owever, it also consumed the most power, and the noise figure was degraded. the second goal was to achieve a balance among iip3 , the noise figure, and power consumption . finally, the third goal was for an optimized noise figure. this configuration resulted in the lowest power consumption while iip3 was not optimized. table 15 summarizes the test conditions; table 16 shows the cor - responding mixer_ rdac, mixer_ cdac, and mixer_bias values. t he resulting iip3 and noise figure performance for the specific mixer_ rdac, mixe r_ cdac, and mixer_bias settings are shown in figure 84 . 0 5 10 15 20 25 30 35 40 45 50 0.6 1.1 1.6 2.1 2.6 iip3 (dbm)/noise figure (db) rf frequenc y (ghz) iip3 noise figure iip3: opt iip3 iip3: opt noise figure iip3: iip3 and noise figure balance nf: opt iip3 nf: opt noise figure nf: iip3 and noise figure balance 1 1489-066 figure 84 . example iip3 and noise figure optimization table 15. mixer optimization summary parameter test conditions/comme nts optimized iip3 mixer_r dac, mixer_ c dac, and mixer_bias were configured for optimized iip3 performance. noise figure, iip3, and power consumption balance mixer_bias was limited to 0, 1, or 2 decimal for improved noise figure while allowing iip3 to degr ade. mixer_r dac and mixer_ c dac were chosen fo r optimized iip3 because mixer_rdac and mixer_cdac have a larger impact on iip3 than on noise figure. optimized noise figure mixer_bias was set to 0 decimal for the best noise figure. mixer_rdac and mixer_cdac were chosen for optimized iip3 because they have a larger impact on iip3 than on noise figure. table 16. recomme nded bal_cin, bal_cout , mixer_r dac, mixer_c dac , and mixer_bias settings (in decimal) rf frequency (mhz) bal_cin bal_cou t optimized iip3 iip3 and noise figure balance optimized n oise f igure r dac c dac bias r dac c dac bias r dac c dac bias 600 7 7 6 10 4 4 15 2 4 15 0 700 7 7 5 14 4 4 15 2 4 15 0 800 5 5 3 13 3 3 14 2 2 15 0 900 3 4 0 15 0 3 13 2 2 14 0 940 3 3 5 12 4 5 11 2 2 13 0 1000 2 3 5 11 4 4 10 2 3 11 0 1100 1 2 5 10 4 3 10 1 2 11 0 1200 1 2 5 9 4 3 9 1 2 10 0 1300 0 2 8 8 4 3 9 1 2 10 0 1400 0 2 6 7 4 4 8 1 2 9 0 1500 0 2 6 7 4 5 7 2 3 8 0 1600 0 2 8 7 4 5 7 2 2 8 0 1700 0 1 6 6 4 5 6 2 4 7 0 1800 0 1 9 6 4 5 6 2 4 7 0 1840 0 1 9 6 5 5 6 2 3 7 0 1900 0 1 9 6 5 6 5 2 3 7 0 2000 0 1 7 5 5 3 6 0 3 6 0 2100 1 1 9 5 5 5 5 1 3 6 0 2140 1 1 9 5 4 5 5 1 3 6 0 2200 2 0 7 4 4 5 5 1 3 6 0 2300 2 0 7 4 4 5 5 1 3 6 0 2400 1 0 7 4 4 5 5 1 3 6 0 2500 1 0 7 4 4 5 5 1 3 6 0 2600 1 0 7 4 4 5 5 1 3 6 0 2700 1 0 7 4 4 5 5 1 3 6 0 2800 1 0 7 4 4 4 15 2 4 15 0 2900 1 0 7 4 4 4 15 2 4 15 0 3000 0 0 7 4 4 3 14 2 2 15 0
data sheet adrf6620 rev. 0 | page 35 of 52 interstage filtering requirements filtering at the mixer output may be necessary for improved linearity performance . for applications where the frequency plan requires low rf frequency inputs and if outputs, the resulting sum term at the mixer outputs, f rf + f lo , may fall within the band of interest. the unwanted sum term may cause the if dga to op erate in its nonlinear region because of the unnecessary presence of additional signal power . as a result, the linearity performance degrade s where oip3 and oip2 decrease substantially. for this reason, a low - pass filter is necessary to attenuate the unwan ted signal while maintaining the integrity of the wanted signal within the band of interest. in addition , the low - pass filter serves to suppress the lo feed through . because of the absence of blockers in a typical dpd receive application, a lower order filt er, such as a third - order chebyshev, is typically adequate. the low - pass filter resides between the mixer output s and the if dga inputs, as shown in figure 85 . the signal flow starts with the di fferential outputs of the mixer be ing dc biased to positive supply (5 v) via a pair of pull - up inductors, l1 and l2. the inductor value is determined by the low frequency cutoff of the signal band of interest. next, t he third - order low - pass filter attenuates the high frequency sum term. th e combination of the pull - up inductors and the low - pass filter result s in a band - pass filter profile. the outputs of the filter are then ac - coupled through series capacitors and routed to the on - chip if dga via the ifin+ and ifin? pins. mxout+ mxout? ifin+ ifin? ifout1? ifout1+ ifout2? ifout2+ rf +5v l2 l1 l3 l4 c1 c2 0.1 f 0.1 f 1 1489-048 lo 18 19 16 15 9 8 11 10 figure 85 . low - pass if filter when designing the low - pass filter, it is important to consider the output impedance of the mixer and the input impedance of the if dga . the output impedance of the mixer has both a real and reactive component, and its equivalent model is shown in figure 86 . correspondingly, figure 87 shows the impedance vs. frequency for the mixer output. mxout+ mxout? 1.1pf 2.5pf 82.5 90 82.5 + + 1 1489-049 figure 86 . equivalent model of the mixer output impe dance 0 1 2 3 4 5 6 7 8 9 10 0 100 200 300 400 500 frequenc y (mhz) 600 700 800 900 1000 150 170 190 210 230 250 270 290 p aralle l ca p aci t ance (pf) p aralle l resis t ance ( ?) p aralle l ca p aci t ance p aralle l resis t ance 1 1489-050 figure 87 . mixer output impedance vs. frequency likewise, figure 88 shows the impedance vs. frequency for the if dga . the four - port s parameter files for the if dga and mixer are available on analog.com and can serve as a useful tool to accurately capture the input and output impedance when designing the interstage filter. as a first - order a pproximation at low frequencies, the mixer output has a fixed impeda nce of approximately 255 , and the input impedance of the if dag is approximately 150 . therefore, design the low - pass filter to have an input impedance of 255 and an output impedance of 150 . 0 50 100 150 200 250 300 350 400 450 500 0 2 4 6 8 10 12 14 16 18 20 0 100 200 300 400 500 600 700 800 900 1000 p aralle l resis t ance ( ?) p aralle l ca p aci t ance (pf) frequenc y (mhz) output ca p aci t ance input ca p aci t ance output resis t ance input resis t ance p aralle l ca p aci t ance p aralle l resis t ance 1 1489-051 figure 88 . if dga input/output impedance vs. frequency
adrf6620 data sheet rev. 0 | page 36 of 52 most important, the low - pass interstage filter must attenuate the sum term (f rf + f lo ) and lo feedthrough to prevent unnecessary overdrive of the dga. the level of attenuation that is required to achieve optimal oip3 performance is shown in figure 89, where oip3 vs. (f rf + f lo ) amplitude is plotted. to maintain performance, attenuate the amplitude of the sum term to at least ?16 dbm (see figure 89 ) . beyond this point, the oip3 degrades decibel per decibel for increased amplitudes. 30 32 34 36 38 40 42 44 46 ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 oip3 (dbm) amplitude (dbm) 1 1489-052 figure 89 . oip3 vs. (f rf + f lo ) amplitude the adrf6620 is optimized for use in digital predistortion (dpd) receivers. an example filter design for dpd is shown in figure 91. table 17 lists the interstage filter design targets. in most dpd systems for cellular transmission, the pass band is between 50 mhz and 500 mhz. for this reason, the pull - up inductors have a low frequency cutoff of 50 mhz, and the pass - band edge of the interstage low - pass filter is 500 mhz. this results in a band - pass filter profile with a maximally flat pass band from 50 mhz to 500 mhz. the stop - band attenuation at 1400 mhz is 20 db, which typically provides the necessary attenuation of the mixer sum term with some margin. table 17. example filter design parameter value r s 255 r l 150 pass - band edge 500 mhz attenuation at pass - band edge 0.5 db stop - band edge 1400 mhz attenuation at stop - band edge 20 db filter type third - order chebyshev using filter equations from a textbook or filter design software, a third - order chebyshev filter can be designed to satisfy all the specifications in table 17 , as shown in figure 91 . the mixer output capacitance of 1.1 pf can be absorbed into the filter , resulting in a reduction in c1 from 2 pf to 0.8 pf. in addition , depending on the pcb b oard stack - up, c2 can be further reduced , or eliminated , because the capacitance of the pcb board can be used as the third pole of the filter. the components used in the simulation were the coi lcraft 0805cs inductors and murata grm15 series capacitors . figure 90 shows the filter profile that satisfies all the filter specifications in table 17 . ? 40 ? 35 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 amplitude (dbm) frequenc y (mhz) 1 1489-054 figure 90 . third - order chebyshev filter profile 1.1pf 2.5pf 82.5 82.5 90 mxout+ r s r l mxout? l3 24nh l4 24nh 0.1 f 0.1 f +5v ifin+ ifin? mixer output impedance equivalent model third-order chebyshev filter dc blocking caps 150 ideal if amp input impedance l1 470nh l2 470nh c1 0.8pf c2 1pf + + + + + + 1 1489-053 figure 91 . low - pass interstage filter design
data sheet adrf6620 rev. 0 | page 37 of 52 maintaining the same third - order chebyshev filter design shown in figure 91 , the component values can be tuned to optimize per formance with some trade - offs. to achieve maximally flat pass - band response, the trade - off is signal bandwidth (see figure 92 ). the l3 and l4 inductor s are replaced with 47 nh, and the capacitors are not populated. this configurat ion results in the flattest pass - band ripple; however, the signal bandwidth starts to roll off at 300 mhz. a narrower bandwidth translates to more attenuation of the mixer sum and lo leakage, which is a desirable effect if the wider signal bandwidth is not a requirement. use the results shown in figure 92 only as a guide, and design the interstage filter to the specific pcb board conditions. the plots in figure 92 were measured using the adrf6620 evaluation board. 4 5 6 7 8 9 10 11 12 50 100 150 200 250 300 350 400 450 500 gain (db) if frequenc y (mhz) l3 = l4 = 47nh, c1 = c2 = open l3 = l4 = 39nh, c1 = c2 = open l3 = l4 = 24nh, c1 = 0.8p f , c2 = 1pf 1 1489-055 figure 92 . interstage filter design trade - offs because the capacitance of the adrf6620 evaluation board closely approximates the c1 and c2 capacitors, they can be removed from the design. however, this may not be the case for every pcb design with different stack - ups. figure 93 compares the oip3 and oip2 performan ce of the adrf6620 with and without filtering at the mixer output. 15 25 35 45 55 65 75 85 50 100 150 200 250 300 350 400 450 500 oip2 (dbm)/oip3 (dbm) if frequenc y (mhz) oip3 with no fi lter oip3 with fi lter oip2 with no fi lter oip2 with fi lter 1 1489-056 figure 93 . oip2/ o ip3 performance with and without filtering at the dga output ; rf frequency = 90 0 mhz; high - side lo i njection , lo sweep
adrf6620 data sheet rev. 0 | page 38 of 52 if dga vs. load by design, the if dga is optimized for performance in a matched condition where the source and load resistances are both 150 . i f the load or the source resistance is not equal to 150 (see the digitally programmable variable gain amplifier (dga) section), use the following equations to determine the resulting gain and input/output resistances : voltage gain = a v = 0.044 (1000|| r l ) r in = (1000 + r l )/(1 + 0.044 r l ) s21 ( gain ) = 2 r in /( r in + r s ) a v r out = (1000 + r s )/(1 + 0.044 r s ) in a configuration where the mixer outputs of the adrf6620 are routed to the if dga inputs , the matched condition is no lo nger satisfied because the source impedance , as seen by the if dga , is the 255 output impedance of the mixer outputs. as a result , the gain and output resista nce of the amplifier var y from the expected 15 db (see figure 94 ). 255 r in r out r l 1 1489-067 figure 94 . mixer loading of the if dga the ideal load is 150 for the matched condition ; however , this may not be the most readily available load impedance. as a result, load vs. performance trade - offs must be considered . in the matched condition , the if dga is optimized for linearity ; therefore , the third - order intermodulation product degrade s with load. table 18 shows some common output loads , and figure 95, figure 96 , and figure 97 show the effect s of loading on gain, imd2, and imd3. as the equations in th is section indicate, the manner in which the if dga is loaded affect s the input resistance, r in , of the amplifier. r in , in turn , determine s the load resista nce of the interstage filter between the mixer outputs and the if dga inputs. the interstage filter ha s a source impedance of 255 from the mixer outputs and a load impedance of r in for the particular r l loa d (see table 18 ). as a result of the impedance mismatch , the insertion loss of the inter stage filter must be included in the level planning calculations. 0 2 4 6 8 10 12 14 16 18 20 0 100 200 300 400 500 600 700 800 900 1000 if dg a gain (db) frequenc y (mhz) r l = 150 r l = 500 r l = 73 r l = 50 1 1489-068 figure 95 . if dga gain vs. frequency for different loads ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 40 120 200 280 360 440 520 600 680 if dg a imd3 (dbc) frequenc y (mhz) r l = 150 r l = 500 r l = 73 r l = 50 1 1489-069 figure 96 . if dga imd3 vs. frequency for different loads ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 40 80 120 160 200 240 280 320 360 400 440 480 520 560 600 640 680 if dg a imd2 (dbc) frequenc y (mhz) 150 ? load 50 ? load 500 ? load 73 ? load 1 1489-070 figure 97 . if dga imd2 vs. frequency for different loads table 18. common output loads r s ( ? ) r in ( ? ) a v (linear) a v (db) s21 (linear) s21 (db) r out ( ? ) r l ( ? ) 255 65 14.7 23.3 6 15.5 102.7 500 255 151 5.7 15.2 4.3 12.6 102.7 150 255 255 3 9.5 3 9.5 102.7 73 255 328 2.1 6.4 2.4 7.5 102.7 50
data sheet adrf6620 rev. 0 | page 39 of 52 adc interfacing the integrated if dga of the adrf6620 provides variable and sufficient drive capability for both buffered and unbuffered adcs. it also provides isolation between the sampling edges of the adc and the mixer core. as resul t, only an antialiasing filter is required when interfacing with an adc . the adrf6620 is optimized for use in cellular base station digital predistortion (dpd) systems . predistortion is used to improve the linearity of transmitter power amplifiers (pa). because the input signal to the dpd path is the known transmitted signal, the hardware specifications are not typically as stringent as the main receive path. the signal - to - noise ratio (snr) of the adc is not paramount , due to the autocorrelation with the known transmitted signal. for this reason, lower resolution adcs are usually adequate , and 11- bit to 14 - bit resolution typically suffices . a more critical consideration is the analog bandwidth of the converter . traditional dpd systems require 3 to 5 the transmit bandwidth. therefore, f or a 100 mhz t x bandwidth, the dpd bandwidth must be at least 500 mhz for fifth - order correction. the ad9434 complements the adrf6620 very well in a dpd design. the ad9434 is a 12 - bit, 370 msps/500 msps buffered adc. its full power analog bandwidth is 1 ghz, making it wide enough for fifth - order correction with substantial margin. the sampling rate of the ad9434 is insufficient in satisfying the sampling theorem ; ho wever, this may be acceptable in dpd applications where under sampling is often permissible . because the receive signal in the dpd path is the known transmitted signal, the desired signal and its aliases are clearly distinguished. the antialiasing filte r r esides between the adrf6620 and the ad9434 . because aliasing is common practice in a dpd receive chain, the antialiasing filter requirements can be relaxed. a second - order or third - order filter is sufficient in reducing the high frequency noise from folding back into the band of interest. when designing the antialiasing filter, it is important to consider the output impedance of th e if dga of the adrf6620 and the input impedance of the ad9434 . the differential resistance of the ad9434 is 1 k, and the parallel capacitance is 1.3 pf. for the matched load condition, where the if dga is optimized for gain and linearity, load the if dga with 150 . to do this, place a 176 resistor in parallel with the input of the adc . the parallel combi nation of the 176 with the 1 k of the adc input impedance results in an equivalent 150 differential output load as seen by the if dga of the adrf6620 . in ad dition , the input capacitance of the ad9434 can be used as the fourth pole of the antialiasing filter. the final schematic design is shown in figure 99 . the antialiasing filter is maximally flat , with a pass - band bandwidth of 500 mhz . table 19 shows the component values for the antialiasing filter design for dpd. figure 98 shows the simulated antialiasing filter design. table 19. component values for 500 mhz antialiasing filter design parameter value type manufacturer l1 = l2 470 nh 0805 cs coilcraft c1 dnp grm15 murata l3 = l4 39 nh 0805 cs coilcraft c2 dnp grm15 murata l5 = l6 1 h 0805 ls coilcraft l7 = l8 15 nh 080 5 cs coilcraft c3 2.7 pf grm15 murata l9 = l10 27 nh 0805 cs coilcraft ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 frequenc y (mhz) amplitude (db) 1 1489-100 figure 98 . simulated antialiasing filter design ad9434 255 adrf6620 mixer output +5v +5v adrf6620 if am p l1 l2 l5 l6 l3 l4 l9 l10 l7 l8 c1 c2 c3 1k 1.3pf 88 88 + + + + + + + + 0.1 f 0.1 f 0.1 f 0.1 f 1 1489-071 figure 99 . adr f6620 interface to the ad9434
adrf6620 data sheet rev. 0 | page 40 of 52 power modes the adrf6620 has many building blocks , and these blocks can be independently powere d off by writing to r egister 0x01 (see table 23 ). external lo mode in external lo mode , the internal pll and vco are disabled , which reduces the current consumption by approximately 100 ma. table 20 lis ts t he register setting s that are required to configure external lo mode . table 20 . serial port configuration for external lo mode bit name state register ldo_3p3_en on 0x01 = 0x8b53 vco_ldo_en on 0x01 = 0x8b53 cp_en off 0x01 = 0 x8b53 div_en off 0x01 = 0x8b53 vco_en on 0x01 = 0x8b53 ref_buf_en off 0x01 = 0x8b53 lo_drv_en off 0x01 = 0x8b53 lo_path_en on 0x01 = 0x8b53 mix_en on 0x01 = 0x8b53 if_amp_en on 0x01 = 0x8b53 lo_ldo_en on 0x01 = 0x8b53 vco_sel external lo 0x22 , bit s [2:0] = 011 if dga disable mode in applications where the if dga is not used , it can be powered down. power - down is achieved by disabling the if_amp_en bit (register 0x01 , bit 11 = 0) . by disabling the amplifier , the current consumption of the adrf6620 decrease s by approxim ately 25 ma , along with a 35 ma to 50 ma current savings through each bias inductor at the output of the amplifier . when the if dga is disabled, its input and output imped ance is h igh - z. for this reason , the input and output pins can be left open. if the preference is not to leave the nodes open, the alternative option is to terminate the pins to ground via a 1 k? resistor. layout careful layout of the adrf6620 is necessary for optimiz ing performance and minimizing stray parasitic s. because t he adrf6620 supports four rf inputs , the layout of the r f section is critical in achieving isolation between each channel. figure 100 shows the recommended layout for the rf inputs. each rf input , rfin0 to rfin3, is isolated between ground pins , and the best layout approach is to keep the traces short and direct. to achie ve this layout , connect the pins direc tly to the center ground pad of the exposed pad of the adrf6620 . this approach minimize s the trace inductance and pr omote s better isolation between the channels. in a dditional, for improved isolation, do not route the rfin0 to rfin3 traces in parallel to each other ; instead, spread the traces immediately after each one leaves the pins. keep t he traces as far away from e ach other as possible ( and at an angle , if possible) to prevent cross coupling. the input impedance of the rf inputs is 50 ? , and the traces leading to the pin must also have a 50 ? characteristic impedance . terminate unused rf inputs with a dc blocking ca p acitor to ground. 1 1489-072 rfin 0 rfin 1 rfin 2 rfin 3 gnd gnd gnd gnd gnd gnd gnd gnd figure 100 . recommended layout for the rf inputs the if dga outputs on the adrf6620 have two output pins for each polarity , and they are ori ented in an alternating fashion, as follows: ifout1+ (p in 8), ifout1 ? (p in 9), ifout2+ (p in 10) , and ifout2? (p in 11). when designing the board , minimize the parasitic capacitance due to the routing that connects the corre - sponding outputs together. a good practice is to avoid any ground or power plane under this routing r egion and under the chokes to minimize the parasitic capacitance. figure 101 sho ws the recommended layout. the if dga output pins with the same polarity are tied together on the bottom of the board with the blue traces and vias . ifout1+ ifout1? ifout2+ ifout2? 1 1489-073 figure 101 . recommended layout for the if dga outputs ( green traces are routings on top of the board , and blue traces are routings on the bottom of the board .)
data sheet adrf6620 rev. 0 | page 41 of 52 register map table 21. register map summary table reg name bits bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reset rw bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 soft_reset [15:8] reserved 0x00000 w [7:0] reserved soft_reset 0x01 enables [15:8] lo_ldo_en reserved reser ved reserved if_amp_en reserved mix_en lo_path_en 0x8b7f rw [7:0] lo_drv_en reserved ref_buf_en vco_en div_en cp_en vco_ldo_en ldo_3p3_en 0x02 int_div [15:8] reserved div_mode int_div[10:8] 0x0058 rw [7:0] int_div[7:0] 0x03 frac_div [15:8] rese rved frac_div[10:8] 0x0250 rw [7:0] frac_div[7:0] 0x04 mod_div [15:8] reserved mod_div[10:8] 0x0600 rw [7:0] mod_div[7:0] 0x20 cp_ctl [15:8] reserved reserved cscale reserved 0x0c26 rw [7:0] reserved bleed_dir bleed 0x21 pfd_ctl [15:8] re served 0x0003 rw [7:0] reserved ref_mux_sel pfd_polarity refsel 0x22 flo_ctl [15:8] reserved lo_drv_lvl[1] 0x000a rw [7:0] lo_drv_lvl[0] reserved lo_div_a vco_sel 0x23 dga_ctl [15:8] reserved rfsw_mux rfsw_sel rfdsa_sel[3] 0x0000 rw [7:0] rf dsa_sel[2:0] if_attn 0x30 balun_ctl [15:8] reserved 0x00000 rw [7:0] bal_cout reserved bal_cin reserved 0x31 mixer_ctl [15:8] reserved mixer_bias mixer_rdac[3] 0x08ef rw [7:0] mixer_rdac[2:0] reserved mixer_cdac 0x40 pfd_ctl2 [15:8] reserved 0x0010 rw [7:0] reserved abldly cpctrl clkedge 0x42 dith_ctl1 [15:8] reserved 0x000e rw [7:0] reserved dith_en dith_mag dith_val 0x43 dith_ctl2 [15:8] dith_val[15:8] 0x0001 rw [7:0] dith_val[7:0]
adrf6620 data sheet rev. 0 | page 42 of 52 register address descriptions register 0x00, reset: 0x00000, name: soft_reset table 22. bit descriptions for soft_reset bit bit name settings description reset access 0 soft_reset soft reset 0x0000 w register 0x01, reset: 0x8b7f, name: enables table 23. bit descriptions for enables bits bit name settings description reset access 15 lo_ldo_en power up lo ldo 0x1 rw 11 if_amp_en if dga enable 0x1 rw 9 mix_en mixer enable 0x1 rw 8 lo_path_en external lo path enable 0x1 rw 7 lo_drv_en lo driver enable 0x0 rw 5 ref_buf_en reference buffer enable 0x1 rw 4 vco_en power up vcos 0x1 rw 3 div_en power up dividers 0x1 rw 2 cp_en power up charge pump 0x1 rw 1 vco_ldo_en power up vco ldo 0x1 rw 0 ldo_3p3_en power up 3.3 v ldo 0x1 rw
data sheet adrf6620 rev. 0 | page 43 of 52 register 0x02, reset: 0x0058, name: int_div table 24. bit descriptions for int_div bits bit name settings description reset access 11 div_mode 0x0 rw 0 fractional 1 integer [10:0] int_div set divider int value 0x58 rw register 0x03, reset: 0x0250, name: frac_div table 25. bit descriptions for frac_div bits bit name settings description reset access [10:0] frac_div set divider frac value 0x250 rw register 0x04, reset: 0x0600, name: mod_div table 26. bit descriptions for mod_div bits bit name settings description reset access [10:0] mod_div set divider mod value 0x600 rw
adrf6620 data sheet rev. 0 | page 44 of 52 register 0x20, reset: 0x0c26, name: cp_ctl table 27. bit descriptions for cp_ctl bits bit name settings description reset access [13:10] cscale charge pump current 0x3 rw 0001 250 a 0011 500 a 0111 750 a 1111 1000 a 5 bleed_dir charge pump bleed direction 0x1 rw 0 sink 1 source [4:0] bleed charge pump bleed 0x06 rw 00000 0 a 00001 15.625 a n 15.625 a 11110 468.75 a 11111 484.375 a
data sheet adrf6620 rev. 0 | page 45 of 52 register 0x21, reset: 0x0003, name: pfd_ctl table 28. bit descriptions for pfd_ctl bits bit name settings description reset access [6:4] ref_mux_sel set ref output divide ratio/vptat/lock_det 0x0 rw 000 lock_det 001 vptat 010 refclk 011 refclk/2 100 refclk 2 101 reserved 110 refclk/4 111 reserved 3 pfd_polarity set pfd polarity 0x0 rw 0 positive k v vco 1 negative k v vco [2:0] refsel set ref input divide ratio 0x3 rw 000 2 001 1 010 div2 011 div4 100 div8
adrf6620 data sheet rev. 0 | page 46 of 52 register 0x22, reset: 0x000a, name: flo_ctl table 29. bit descriptions for flo_ctl bits bit name settings description reset access [8:7] lo_drv_lvl lo amplitude 0x0 rw 00 ?4 dbm 01 0.5 dbm 10 +3 dbm 11 +4.5 dbm [4:3] lo_div_a lo_div_a 0x1 rw 00 div1 01 div2 10 div4 11 div8 [2:0] vco_sel select vco core/external lo 0x2 rw 000 5.2 ghz to 5.7 ghz 001 4.1 ghz to 5.2 ghz 010 2.8 ghz to 4.1 ghz 011 ext lo 100 vco_pwrdwn 101 vco_pwrdwn 110 vco_pwrdwn 111 vco_pwrdwn
data sheet adrf6620 rev. 0 | page 47 of 52 register 0x23, reset: 0x0000, name: dga_ctl table 30. bit descriptions for dga_ctl bits bit name settings description reset access 11 rfsw_mux set switch control. 0x0 rw 0 serial cntrl 1 pin cntrl [10:9] rfsw_sel set rf input. 0x0 rw 00 rfin0 01 rfin1 10 rfin2 11 rfin3 [8:5] rfdsa_sel set rfdsa attenuation. range: 0 db to 15 db in steps of 1 db. 0x0 rw 0000 0 db 0001 1 db ... 1110 14 db 1111 15 db [4:0] if_attn if attenuation. range: 3 db to 15 db in steps of 0.5 db. 0x0 rw 00000 3 db 00001 3.5 db ... 10111 14.5 db 11000 15 db
adrf6620 data sheet rev. 0 | page 48 of 52 register 0x30, reset: 0x00000, name: balun_ctl table 31. bit descriptions for balun_ctl bits bit name settings description reset access [7:5] bal_cout set balun output capacitance 0x0 rw 000 minimum capacitance ... ... 111 maximum capacitance [3:1] bal_cin set balun input capacitance 0x0 rw 000 minimum capacitance ... ... 111 maximum capacitance register 0x31, reset: 0x08ef, name: mixer_ctl table 32. bit descriptions for mixer_ctl bits bit name settings description reset access [11:9] mixer_bias set mixer bias value 0x4 rw 000 minimum ... 111 maximum [8:5] mixer_rdac set mixer rdac value 0x7 rw [3:0] mixer_cdac set mixer cdac value 0xf rw
data sheet adrf6620 rev. 0 | page 49 of 52 register 0x40, reset: 0x0010, name: pfd_ctl2 table 33. bit descriptions for pfd_ctl2 bits bit name settings description reset access [6:5] abldly set antibacklash delay 0x0 rw 00 0 ns 01 0.5 ns 10 0.75 ns 11 0.9 ns [4:2] cpctrl set charge pump control. 0x4 rw 000 both on 001 pump down 010 pump up 011 tristate 100 pfd [1:0] clkedge set pfd edge sensitivity 0x0 rw 00 div and ref down edge 01 div down edge, ref up edge 10 div up edge, ref down edge 11 div and ref up edge
adrf6620 data sheet rev. 0 | page 50 of 52 register 0x42, reset: 0x000e, name: dith_ctl1 table 34. bit descriptions for dith_ctl1 bits bit name settings description reset access 3 dith_en set dither enable 0x1 rw 0 disable 1 enable [2:1] dith_mag set dither magnitude 0x3 rw 0 dith_val set dither value 0x0 rw register 0x43, reset: 0x0001, name: dith_ctl2 table 35. bit descriptions for dith_ctl2 bits bit name settings description reset access [15:0] dith_val set dither value 0x1 rw
data sheet adrf6620 rev. 0 | page 51 of 52 outline dimensions compliant to jedec standards mo-220- wkkd . for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 0.50 bsc bot t om view top view pin 1 indic at or 48 13 24 36 37 exposed pa d pin 1 indic at or 5.65 5.50 sq 5.35 0.45 0.40 0.35 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.23 0.18 06-06-2012-b 7.10 7.00 sq 6.90 0.20 min 5.50 ref figure 102 . 48 - lead lead frame chip scale package [lfcsp_ wq ] 7 mm 7 mm body, very very thin quad (cp - 48 -9) dimensions shown in millimeters ordering guide model 1 temperature range package description pa ckage option adrf6620acpz -r7 ?40c to +85c 48- lead lead frame chip scale package [lfcsp_wq] cp -48 -9 adrf6620 - evalz evaluation board 1 z = rohs compliant part.
adrf6620 data sheet rev. 0 | page 52 of 52 notes ? 2013 analog devices, inc. all rights reserved. trademarks and registere d trademarks are the property of their respective owners. d11489 -0- 7/13(0)

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